Projects

Z2: Validation and Demonstrator

Principal Investigators:

Prof. J. Becker, PD Dr. F. Hannig, Dr. T. Wild

Scientific Researchers:

N. Anantharajaiah, M. Brand, C. Heidorn, F. Lesniak, S. Rheindt, A. Srivatsa

Abstract

The major goal of Project Z2 is to support the demonstration of the research challenges of our CRC's third funding phase, both simulation-based as well as on FPGA-based hardware platform designs. These vital demonstrators will cover all relevant layers of invasive computing, from the level of hardware to system software and algorithmic concepts of invasive applications. As the contributions of the different projects are heavily intertwined, the associated parts have to be integrated and assembled into comprehensive demonstrators.

In the first funding phase and the second funding phase, a common FPGA-based demonstrator environment was created in order to enable the prototyping of heterogeneous invasive multi-tile MPSoC designs, and thus, debugging and validation of the concepts of invasive computing. The contributions of the different projects across all project areas were integrated into one platform in order to demonstrate the advantages of invasive computing such as improved quality of service, resource utilisation and speed-up of applications. In the second funding phase a ProDesign proFPGA system was purchased, installed and is heavily used at each site (FAU, KIT, TUM) as the validation and demonstration platform. Thanks to its capacity of four Xilinx Virtex-7 2000T FPGAs, the system allows for prototyping of multi-million gate designs, and thus, hardware prototypes of novel invasive multicore architectures as investigated in project area B. We developed the necessary components to integrate peripherals like UART, SSRAM, Ethernet and DDR3 Memory into the common demonstrator and established the appropriate tool support for the proFPGA system. In addition to prototyping, the proFPGA platform has shown enormous benefits for co-simulation/emulation and transaction-based verification. In order to ease the debugging of each invasive multi-tile MPSoC design during the integration phase as well as when testing it, we used the above capabilities and built a comprehensive debugging system on top of it. And finally, we gave support to the projects integrating their components into the common demonstrator on the proFPGA.

In the third funding phase, Project Z2 will continue in providing support for demonstrating the benefits of invasive computing across all involved layers, from algorithmic concepts, software and invasive hardware. Project Z2 will establish the generic infrastructure as required for verification and evaluation of any invasive multi-tile architecture by integrating the various HW/SW components from different projects. Special focus will be on supporting the assessment of the major goals of the overall CRC in the third funding phase, such as enforcement of non-functional properties (e.g. by enforcer automatons Project A1) and verification of properties and constraints at run-time (see e.g. Project B2, Project B3, and Project B4). To support investigating the power efficiency of invasive architectures, power models of the individual components will be emulated and aggregated on the demonstrator platform as well.
As an additional task, Project Z2 will take over the development and extension of the simulation framework InvadeSIM, as a continuation of the work in Project C2. This will be important to test the investigated novel methodologies quickly. Finally, Project Z2 will provide support for the visualisation of results from the simulator as well as the prototyping platforms, helping to establish a unified way to demonstrate and present the results and benefits of invasive computing as early as possible.

Synopsis

The major goal of Project Z2 in the third funding phase of the CRC is also the demonstration of benefits of invasive computing on a real hardware platform, into which contributions from all projects will be integrated. This demonstrator will cover all relevant layers of invasive computing, from the level of hardware to system software and algorithmic concepts of invasive applications. Project Z2 will provide special support to show aspects on the demonstration platform related to the special focal points that are addressed in this funding period, enforcement and verification of non-functional properties, such as performance, security, dependability and energy.

To optimise the integration process of the hardware and software contributions into a common demonstrator, Project Z2 will provide special support for debugging the components and their interaction based on the means offered by the available prototyping platform. In this context, Project Z2 will also provide means for optimised cooperation among the staff members of all CRC projects for testing and verifying components on the demonstrator platform, which has already been started in the first funding phase of the CRC/Transregio.

Special focus will also be given to the visualisation of invasion-specific aspects at system run time to highlight the interaction of the components and the overall system status when invasive applications are executed on the demonstrator.

Approach

Evaluating architectural innovations is a very time-intensive task. In particular for complex multiprocessor systems like an invasive multi-tile architecture (see e.g. figure below), a robust prototyping platform and run-time debug support is essential.

4x4 tile architecture on proFPGA system

For this purpose, a proFPGA system from ProDesign, shown right in the figure, was acquired for each of the sites (FAU, KIT and TUM). It contains four Virtex-7 2000T FPGAs and allows for the prototyping of multi-million gate designs. In addition, it enables co-simulation/emulation and transaction-based verification.

In cooperation with all projects and the working groups of the CRC, tiled invasive compute architectures, such as the one shown in the above figure on the left, were developed and prototyped for the demonstration of invasive applications from the D projects covering robotics and scientific computing, which make up the common demonstration scenarios. The specified platform consists of standard components and specific hardware or system software contributions by the projects to enable invasive computing.

The left part of the figure above shows an example configuration of an invasive MPSoC: A tiled architecture consisting of RISC-processor–based compute tiles (using LEON3 processor cores or the i-Core as developed from Project B1), compute tiles based on TCPAs (tightly-coupled processor array) as developed in Project B2 as well as I/O and memory tiles. The tiles which contain contributions from all projects of project area B are connected via the iNoC. OctoPOS and iRTSS are running on top of this hardware platform. Within Project Z2, such a heterogeneous hardware architecture, the associated system software and the invasive applications on top were integrated on the FPGA prototyping system.

Project Z2 contributes in the following three major ways in the realisation of the overall demonstrator:

  • Provisioning the basic infrastructure required to realise the common demonstrator on the proFPGA system. This consists of generic hardware components not specific to invasive computing (like common peripherals and controllers) and of the proFPGA-specific tool and design flow support.
  • Supporting the integration of the different projects’ contributions, i.e. hardware and software components, into the common demonstrator.
  • Coordination work for the definition of demonstrator scenarios on the prototyping system, including milestone planning.

Project Z2 will continue its central role in providing the required support for demonstrating the benefits and properties of invasive computing across all project areas. That is, the demonstration platform not only provides the required testbed for validation for projects from area B from but also for the evaluation of software and algorithmic concepts from project areas C and A, respectively. Project Z2 will provide a generic infrastructure as required for the demonstrator platform as well as coordinate and integrate the various HW/SW components from different projects into a common demonstrator. Compared to the first two funding phases, the tasks of Project Z2 will be:

  1. Project Z2 will maintain the established generic FPGA-based demonstration platform (including both tools and hardware components) and will allow to easily switch between stable configurations, i.e. architecture variants in order to provide invasive hardware platforms to projects from area C and D from the early beginning of the third funding phase. Similarly, Project Z2 will provide an x86-based multicore system (> 64 cores) with an iRTSS port (from Project C1) to all software and application projects. For both FPGA-based and x86-based, appropriate (shared) directory structures, version management, remote access and coordination of access will be provided. Project Z2 will contribute the required support for verification and testing with respect to the major goals of the overall CRC in the third funding phase, which are Run-time verification and enforcement of non-functional program requirements.
  2. The system-level simulator InvadeSIM, which has been developed by Project C2, has been one major and operative instrument in the first two funding phases. Particularly in project areas A and D, it has been and is still used for first implementation and testbed of all our programming concepts such as InvadeX10 and actor-oriented programming (ActorX10) as well as a basis for architecture exploration and application mapping. Naturally, InvadeSIM will continue this important role in the third funding phase. Based on this simulation framework, the novel ideas and techniques, particularly on enforcement of non-functional properties of program execution, will find their first implementation and proof of concept.
  3. Initialising and coordination of a digital long-term preservation of all developed hardware and software throughout the three funding phases.

Further information about the first and second funding phase can be found by accessing Project Z2 first phase web page and Project Z2 second phase web page, respectively.

Publications

[1] Jürgen Becker, Frank Hannig, Thomas Wild, Marcel Brand, Oliver Lenke, and Fabian Lesniak. Validation and demonstrator. In Jürgen Teich, Jörg Henkel, and Andreas Herkersdorf, editors, Invasive Computing, pages 411–431. FAU University Press, August 16, 2022. [ DOI ]
[2] Nidhi Anantharajaiah, Tamim Asfour, Michael Bader, Lars Bauer, Jürgen Becker, Simon Bischof, Marcel Brand, Hans-Joachim Bungartz, Christian Eichler, Khalil Esper, Joachim Falk, Nael Fasfous, Felix Freiling, Andreas Fried, Michael Gerndt, Michael Glaß, Jeferson Gonzalez, Frank Hannig, Christian Heidorn, Jörg Henkel, Andreas Herkersdorf, Benedict Herzog, Jophin John, Timo Hönig, Felix Hundhausen, Heba Khdr, Tobias Langer, Oliver Lenke, Fabian Lesniak, Alexander Lindermayr, Alexandra Listl, Sebastian Maier, Nicole Megow, Marcel Mettler, Daniel Müller-Gritschneder, Hassan Nassar, Fabian Paus, Alexander Pöppl, Behnaz Pourmohseni, Jonas Rabenstein, Phillip Raffeck, Martin Rapp, Santiago Narváez Rivas, Mark Sagi, Franziska Schirrmacher, Ulf Schlichtmann, Florian Schmaus, Wolfgang Schröder-Preikschat, Tobias Schwarzer, Mohammed Bakr Sikal, Bertrand Simon, Gregor Snelting, Jan Spieck, Akshay Srivatsa, Walter Stechele, Jürgen Teich, Furkan Turan, Isaías A. Comprés Ureña, Ingrid Verbauwhede, Dominik Walter, Thomas Wild, Stefan Wildermann, Mario Wille, Michael Witterauf, and Li Zhang. Invasive Computing. FAU University Press, August 16, 2022. [ DOI ]
[3] T. K. R. Arvind, Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, and Jürgen Teich. Hardware implementation of hyperbolic tangent activation function for floating point formats. In Proceedings of the 24th International Symposium on VLSI Design and Test (VDAT). IEEE, July 2020. [ DOI ]
[4] Frank Hannig, Javier Navaridas, Dirk Koch, and Ameer Abdelhadi, editors. Proceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE Computer Society, July 2020. [ DOI ]
[5] Marcel Brand, Michael Witterauf, Alberto Bosio, and Jürgen Teich. Anytime floating-point addition and multiplication – Concepts and implementations. In Proceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 157–164. IEEE, July 2020. [ DOI ]
[6] Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann, and Jürgen Teich. A bibliometric approach for detecting the gender gap in computer science. Communications of the ACM (CACM), 63(5):74–80, May 2020. [ DOI ]
[7] Marcel Brand, Michael Witterauf, Frank Hannig, and Jürgen Teich. Anytime instructions for programmable accuracy floating-point arithmetic. In Proceedings of the ACM International Conference on Computing Frontiers (CF), pages 215–219. ACM, April 2019. [ DOI ]
[8] Efstathios Sotiriou-Xanthopoulos, Leonard Masing, Sotirios Xydis, Kostas Siozios, Jürgen Becker, and Dimitrios Soudris. Opencl-based virtual prototyping and simulation of many-accelerator architectures. ACM Trans. Embed. Comput. Syst., 17(5):86:1–86:27, September 2018. [ DOI ]
Keywords: OpenCL, TLM, co-simulation, distributed memory, fixed-point arithmetic, half-floating-point arithmetic, many-accelerator, memory analysis, parallel architectures, systemC
[9] Éricles R. Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, and Jürgen Teich. Invasive computing for predictability of multiple non-functional properties: A cyber-physical system case study. In Proceedings of the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, July 2018. [ DOI ]
[10] Andreas Weichslgartner, Stefan Wildermann, Michael Glaß, and Jürgen Teich. Invasive Computing for Mapping Parallel Programs to Many-Core Architectures. Springer, January 15, 2018. [ DOI ]
[11] Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann, and Jürgen Teich. The gender gap in computer science — A bibliometric analysis, 2018. [ DOI ]
[12] Stephanie Friederich. Automated Hardware Prototyping for 3D Networks on Chips. Dissertation, Institut für Technik der Informationsverarbeitung, Karlsruhe Institute of Technology (KIT), May 23, 2017.
[13] Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles R. Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, and Jörg Henkel. Resource-awareness on heterogeneous MPSoCs for image processing. Journal of Systems Architecture, 61(10):668–680, November 6, 2015. [ DOI ]
[14] Frank Hannig and Andreas Herkersdorf. Introduction to the special issue on testing, prototyping, and debugging of multi-core architectures. Journal of Systems Architecture, 61(10):600, November 7, 2015. [ DOI ]
[15] Michael Dreschmann, Jan Heisswolf, Michael Geiger, Manuel Haußecker, and Jürgen Becker. A framework for multi-FPGA interconnection using multi gigabit transceivers. In Proceedings of the 28th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 5:1–5:6. ACM, August 2015. [ DOI ]
[16] Johny Paul, Walter Stechele, Éricles R. Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, and Tamim Asfour. Self-adaptive harris corner detector on heterogeneous many-core processor. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP). IEEE, October 2014. [ DOI ]
[17] Stephanie Friederich, Jan Heisswolf, and Jürgen Becker. Hardware/software debugging of large scale many-core architectures. In Proceedings of the 27th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 1–7. IEEE, September 2014. [ DOI ]
[18] Éricles Sousa, Vahid Lari, Johny Paul, Frank Hannig, Jürgen Teich, and Walter Stechele. Resource-aware computer vision application on heterogeneous multi-tile architecture. Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March 2014.
[19] Stephanie Friederich, Jan Heisswolf, David May, and Jürgen Becker. Hardware prototyping and software debugging of multi-core architectures. In Proceedings of the Synopsys Users Group Conference (SNUG), 2014.
[20] Vahid Lari, Srinivas Boppu, Frank Hannig, Jürgen Teich, and Troy Scott. Hybrid prototyping of tightly-coupled processor arrays for MPSoC designs. Designer Track Poster Presentation at the 50th Design Automation Conference (DAC), Austin, TX, USA, June 2013.
[21] Srinivas Boppu, Vahid Lari, Frank Hannig, and Jürgen Teich. Transactor-based prototyping of heterogeneous multiprocessor system-on-chip architectures. In Proceedings of the Synopsys Users Group Conference (SNUG), May 14, 2013.
[22] Vahid Lari, Srinivas Boppu, Frank Hannig, Shravan Muddasani, Boris Kuzmin, and Jürgen Teich. Resource-aware video processing on tightly-coupled processor arrays. Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Grenoble, France, March 2013. [ .pdf ]
[23] Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari, and Jürgen Teich. A prototype of an invasive tightly-coupled processor array. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pages 393–394. IEEE, October 2012.
[24] Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf Koenig, and David May. Hardware prototyping of novel invasive multicore architectures. In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 201–206, January 2012. [ DOI ]