Publications


Publication TypeYearAuthor

2024

[2] Khalil Esper, Stefan Wildermann and Jürgen Teich. Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs. In Design, Automation and Test in Europe Conference, 24- 27 March, 2024, Valencia, Spain, 2024.
[1] Khalil Esper and Jürgen Teich. History-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs. In Fifth Workshop on Next Generation Real-Time Embedded Systems, NG-RES 2024, January 19, 2024, Munich, Germany, 2024.

2023

[5] Martñn Letras, Joachim Falk and Jürgen Teich. Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers. In Fourth Workshop on Next Generation Real-Time Embedded Systems, NG-RES 2023, January 18, 2023, Toulouse, France, pages 6:1–6:13. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2023. [ DOI ] [ http ]
[4] Jan Spieck, Pierre-Louis Sixdenier, Khalil Esper, Stefan Wildermann and Jürgen Teich. Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers. In 21st ACM-IEEE International Symposium on Formal Methods and Models for System Design, MEMOCODE 2023, Hamburg, Germany, September 21-22, 2023, pages 23–35. ACM / IEEE, 2023.
[3] Khalil Esper, Stefan Wildermann and Jürgen Teich. Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms. ACM Trans. Design Autom. Electr. Syst., 28(6):98:1–98:20, 2023. [ DOI ] [ http ]
[2] Khalil Esper, Jan Spieck, Pierre-Louis Sixdenier, Stefan Wildermann and Jürgen Teich. RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs. In Fourth Workshop on Next Generation Real-Time Embedded Systems, NG-RES 2023, January 18, 2023, Toulouse, France, pages 7:1–7:16. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2023. [ DOI ] [ http ]
[1] Jan Spieck, Stefan Wildermann and Jürgen Teich. A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs. ACM Trans. Design Autom. Electr. Syst., 28(1):4:1–4:40, 2023. [ DOI ] [ http ]

2022

[24] Yakup Budanaz, Mario Wille and Michael Bader. Asynchronous Workload Balancing through Persistent Work-Stealing and Offloading for a Distributed Actor Model Library. In 2022 IEEE/ACM Parallel Applications Workshop: Alternatives To MPI+X (PAW-ATM), pages 39-51, November 14, 2022. [ DOI ]
[23] Jan Spieck, Stefan Wildermann and Jürgen Teich. On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures. In CODES+ISSS 2022, October 2022.
[22] Jürgen Teich and Jörg Henkel and Andreas Herkersdorf, editors. Invasive Computing. FAU University Press, 2022. [ DOI ]
[21] Jürgen Teich, Marcel Brand, Frank Hannig, Christian Heidorn, Dominik Walter and Michael Witterauf. Invasive Tightly-Coupled Processor Arrays. In Invasive Computing, 2022, FAU University Press, pages 177–202. [ DOI ]
[20] Gregor Snelting, Jürgen Teich, Andreas Fried, Frank Hannig and Michael Witterauf. Compilation and Code Generation for Invasive Programs. In Invasive Computing, 2022, FAU University Press, pages 309–333. [ DOI ]
[19] Jürgen Becker, Frank Hannig, Thomas Wild, Marcel Brand, Oliver Lenke and Fabian Lesniak. Validation and Demonstrator. In Invasive Computing, 2022, FAU University Press, pages 411–431. [ DOI ]
[18] Lars Bauer, Jörg Henkel, Timo Hönig, Wolfgang Schröder-Preikschat, Christian Eichler, Jeferson Gonzalez, Benedict Herzog, Tobias Langer, Sebastian Maier, Jonas Rabenstein, Phillip Raffeck and Florian Schmaus. Invasive Run-Time Support System (iRTSS). In Invasive Computing, 2022, FAU University Press, pages 285–308. [ DOI ]
[17] Christian Heidorn, Nicolai Meyerhöfer, Christian Schinabeck, Frank Hannig and Jürgen Teich. Hardware-Aware Evolutionary Filter Pruning. In International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), July 2022. [ DOI ]
[16] Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Jörg Henkel and Ulf Schlichtmann. An FPGA-Based Approach to Evaluate Thermal and Resource Management Strategies of Many-Core Processors. ACM Trans. Archit. Code Optim., 19(3):May 2022.
[15] Volker Wenzel, Lars Bauer, Wolfgang Schröder-Preikschat and Jörg Henkel. Agent-based Constraint Solving for Resource Allocation in Manycore Systems. April 2022. [ DOI ] [ http ]
[14] Martin Hecker, Simon Bischof and Gregor Snelting. On Time-Sensitive Control Dependencies. ACM Trans. Program. Lang. Syst., 44(1):1–37, March 2022. [ DOI ] [ http ]
[13] Hassan Nassar, Lars Bauer and Jörg Henkel. CaPUF: Cascaded PUF Structure for Machine Learning Resiliency. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022.
[12] Behnaz Pourmohseni, Stefan Wildermann, Fedor Smirnov, Paul Meyer and Jürgen Teich. Task Migration Policy for Thermal-Aware Dynamic Performance Optimization in Many-Core Systems. IEEE Access, 2022. [ DOI ]
[11] Jan Spieck, Stefan Wildermann and Jürgen Teich. A Learning-Based Methodology for Scenario-Aware Mapping of Soft Real-Time Applications onto Heterogeneous MPSoCs. ACM Transactions on Design Automation of Electronic Systems, 2022. [ DOI ]
[10] Alexandra Listl, Daniel Mueller-Gritschneder and Ulf Schlichtmann. Application-aware aging analysis and mitigation for SRAM Design-for-Relability. Microelectronics Reliability, 134:114548, 2022. [ DOI ] [ http ]
[9] Martin Rapp. Machine Learning for Resource-Constrained Computing Systems. Dissertation, Chair of Embedded Systems, Department of Informatics, Karlsruhe Institute of Technology, Germany, 2022.
[8] Martin Rapp, Nikita Krohmer, Heba Khdr and Jörg Henkel. NPU-Accelerated Imitation Learning for Thermal- and QoS-Aware Optimization of Heterogeneous Multi-Cores. In Design, Automation & Test in Europe (DATE), 2022.
[7] Mohammed Bakr Sikal, Heba Khdr, Martin Rapp and Jörg Henkel. Thermal- and Cache-Aware Resource Management based on ML-Driven Cache Contention Prediction. In Design, Automation & Test in Europe (DATE), 2022.
[6] Martin Rapp, Hussam Amrouch, Yibo Lin, Bei Yu, David Z Pan, Marilyn Wolf and Jörg Henkel. MLCAD: A Survey of Research in Machine Learning for CAD (Keynote Paper). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022.
[5] Khalil Esper, Stefan Wildermann and Jürgen Teich. Multi-requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study (to appear). In Proceedings of the Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2022), 2022.
[4] Tobias Langer. Memory Management in Massive Parallel Non-Coherent Systems. Upcoming Dissertation, Lehrstuhl für Verteilte Systeme und Betriebssysteme, Department Informatik, Friedrich-Alexander-Universität Erlangen-Nürnberg, 2022.
[3] Alexander Lindermayr, Nicole Megow and Bertrand Simon. Double Coverage with Machine-Learned Advice. In ITCS, pages 99:1–99:18. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2022.
[2] Alexander Lindermayr and Nicole Megow. Non-Clairvoyant Scheduling with Predictions Revisited. CoRR, abs/2202.101992022.
[1] Marcel Brand, Frank Hannig, Oliver Keszocze and Jürgen Teich. Precision- and Accuracy-Reconfigurable Processor Architectures – An Overview. IEEE Transactions on Circuits and Systems II: Express Briefs, 69(6):2661-2666, 2022. [ DOI ]

2021

[45] Dominik Walter and Jürgen Teich. LION: Real-Time I/O Transfer Control for Massively Parallel Processor Arrays. In Proceedings of the 19th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), pages 32–43. Association for Computing Machinery, November 2021. [ DOI ]
[44] Florian Schmaus, Florian Fischer, Timo Hönig and Wolfgang Schröder-Preikschat. Modern Concurrency Platforms Require Modern System-Call Techniques. Technical Report CS-2021-02, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Department Informatik, 2021. [ DOI ] [ http ]
[43] Jürgen Teich. Enforcement of Non-functional Program Requirements on MPSOCs. Keynote, HiPEAC Computing Week, Lyon, France, October 25, 2021.
[42] Michael Witterauf. A Compiler for Symbolic Code Generation for Tightly Coupled Processor Arrays. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2021.
[41] Armin Schuster, Christian Heidorn, Marcel Brand, Oliver Keszöcze and Jürgen Teich. Design Space Exploration of Time, Energy, and Error Rate Trade-offs for CNNs using Accuracy-Programmable Instruction Set Processors. In Joint European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases (ECML PKDD), September 2021. [ DOI ]
[40] Jan Spieck, Stefan Wildermann and Jürgen Teich. Domain-Adaptive Soft Real-Time Hybrid Application Mapping for MPSoCs. In 2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD), September 2021.
[39] Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig and Jürgen Teich. Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. In Proceedings of the 31st International Conference on Field-Programmable Logic and Applications (FPL), pages 388. IEEE, August 2021. [ DOI ]
[38] Benedict Herzog, Fabian Hügel, Stefan Reif, Timo Hönig and Wolfgang Schröder-Preikschat. Automated Selection of Energy-efficient Operating System Configurations. In Proceedings of the 2nd International Workshop on Energy-Efficient Learning at the Edge (WEEE'21), 2021.
[37] Florian Schmaus, Nicolas Pfeiffer, Timo Hönig, Jörg Nolte and Wolfgang Schröder-Preikschat. Nowa: A Wait-Free Continuation-Stealing Concurrency Platform. In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), pages 360-371, 05 2021. [ DOI ]
[36] Oliver Lenke, Richard Petri, Thomas Wild and Andreas Herkersdorf. PEPERONI: Pre-Estimating the Performance of Near-Memory Integration. In MEMSYS'21: The International Symposium on Memory Systems, 2021.
[35] Benedict Herzog, Stefan Reif, Julian Preis, Timo Hönig and Wolfgang Schröder-Preikschat. The Price of Meltdown and Spectre: Energy Overhead of Mitigations at Operating System Level. In Proceedings of the 14th European Workshop on Systems Security (EuroSec'21), 2021. [ DOI ]
[34] Mark Sagi, Martin Rapp, Heba Khdr, Yizhe Zhang, Nael Fasfous, Nguyen Anh Vu Doan, Thomas Wild, Jörg Henkel and Andreas Herkersdorf. Long Short-Term Memory Neural Network-based Power Forecasting of Multi-Core Processors. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) , 2021.
[33] Hassan Nassar, Lars Bauer and Jörg Henkel. TiVaPRoMi: Time-Varying Probabilistic Row-Hammer Mitigation. In Design, Automation, and Test in Europe (DATE), 2021.
[32] Nael Fasfous, Manoj-Rohit Vemparala, Alexander Frickenstein, Mohamed Badawy, Felix Hundhausen, Julian Höfer, Naveen-Shankar Nagaraja, Christian Unger, Hans-Jörg Vögel, Jürgen Becker, Tamim Asfour and Walter Stechele. Binary-LoRAX: Low-power and Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands. In International Conference on Robotics and Automation (ICRA), 2021. [ http ]
[31] Oliver Keszöcze, Marcel Brand, Michael Witterauf, Christian Heidorn and Jürgen Teich. Aarith: An Arbitrary Precision Number Library. In ACM/SIGAPP Symposium On Applied Computing, 2021. [ DOI ]
[30] Grace Li Zhang, Bing Li, Ying Zhu, Tianchen Wang, Yiyu Shi, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Tsung-Yi Ho and Ulf Schlichtmann. Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks. In ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 18-21, 2021, pages 853–858. ACM, 2021. [ DOI ] [ http ]
[29] Martin Letras, Joachim Falk, Tobias Schwarzer and Jürgen Teich. Multi-Objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements. ACM Trans. Des. Autom. Electron. Syst., 26(3):2021. [ DOI ]
[28] Behnaz Pourmohseni. System-Level Mapping, Analysis, and Management of Real-Time Applications in Many-Core Systems. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2021.
[27] Khalil Esper, Stefan Wildermann and Jürgen Teich. A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems. In Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021), pages 1–12, 2021. [ DOI ]
[26] Akshay Srivatsa, Mostafa Mansour, Sven Rheindt, Dirk Gabriel, Thomas Wild and Andreas Herkersdorf. DynaCo: Dynamic Coherence Management for Tiled Manycore Architectures. International Journal of Parallel Programming, January 2021. [ DOI ] [ http ]
[25] Akshay Srivatsa, Nael Fasfous, Nguyen Anh Vu Doan, Sebastian Nagel, Thomas Wild and Andreas Herkersdorf. Exploring a Hybrid Voting-based Eviction Policy for Caches and Sparse Directories on Manycore Architectures. Microprocessors and Microsystems, :104384, 2021. [ DOI ] [ http ]
[24] Nidhi Anantharajaiah, Zhe Zhang and Juergen Becker. Multi-layered NoCs with Adaptive Routing for Mixed Criticality Systems. In Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing, 2021. [ DOI ]
[23] Nidhi Anantharajaiah, Felix Knopf and Juergen Becker. Ant Colony Optimization Based NoCs for Flexible Spatial Isolation in Mixed Criticality Systems. In 2021 IEEE 34th International System-on-Chip Conference (SOCC), pages 248-253, 2021. [ DOI ]
[22] Martin Rapp, Mohammed Bakr Sikal, Heba Khdr and Jörg Henkel. SmartBoost: Lightweight ML-Driven Boosting for Thermally-Constrained Many-Core Processors. In Design Automation Conference (DAC), 2021.
[21] Zehang Weng, Fabian Paus, Anastasiia Varava, Hang Yin, Tamim Asfour and Danica Kragic. Graph-based Task-specific Prediction Models for Interactions between Deformable and Rigid Objects. In IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), pages 5453–5460, 2021.
[20] Tanfer Alan, Andreas Gerstlauer and Jörg Henkel. Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021.
[19] Michael Witterauf, Dominik Walter, Frank Hannig and Jürgen Teich. Symbolic Loop Compilation for Tightly Coupled Processor Arrays. ACM Transactions on Embedded Computing Systems (TECS), 2021.
[18] Martin Böhm, Nicole Megow and Jens Schlöter. Throughput Scheduling with Equal Additive Laxity. In CIAC, pages 130–143. Springer, 2021.
[17] Franziska Eberle, Ruben Hoeksma, Nicole Megow, Lukas Nölke, Kevin Schewior and Bertrand Simon. Speed-Robust Scheduling - Sand, Bricks, and Rocks. In IPCO, pages 283–296. Springer, 2021.
[16] Lin Chen, Nicole Megow, Roman Rischke, Leen Stougie and José Verschae. Optimal algorithms for scheduling under time-of-use tariffs. Ann. Oper. Res., 304(1):85–107, 2021.
[15] Angel Villar-Corrales, Franziska Schirrmacher and Christian Riess. Deep Learning Architectural Designs for Super-Resolution Of Noisy Images. In IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2021, Toronto, ON, Canada, June 6-11, 2021, pages 1635–1639. IEEE, 2021. [ DOI ]
[14] Khalil Esper, Stefan Wildermann and Jürgen Teich. Enforcement FSMs: specification and verification of non-functional properties of program executions on MPSoCs. In MEMOCODE '21: 19th ACM-IEEE International Conference on Formal Methods and Models for System Design, Virtual Event, China, November 20 - 22, 2021, pages 21–31. ACM, 2021. [ DOI ]
[13] Johannes Bechberger and Alexander Weigl. Upper Bound Computation of Information Leakages for Unbounded Recursion. In Software Engineering and Formal Methods, pages 160–177. Springer International Publishing, 2021. [ DOI ] [ http ]
[12] Gabor Drescher. Adaptive Address-Space Management for Resource-Aware Applications. Dissertation, Lehrstuhl für Verteilte Systeme und Betriebssysteme, Department Informatik, Friedrich-Alexander-Universität Erlangen-Nürnberg, 2021. [ http ]
[11] Simon Schuster, Peter Wägemann, Peter Ulbrich and Wolfgang Schröder-Preikschat. Annotate Once – Analyze Anywhere: Context-Aware WCET Analysis by User-Defined Abstractions. In Proceedings of the 22nd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES '21, pages 54–66. Association for Computing Machinery, 2021. [ DOI ]
[10] Steffen Vaas, Peter Ulbrich, Christian Eichler, Peter Wägemann, Marc Reichenbach and Dietmar Fey. Taming Non-Deterministic Low-Level I/O: Predictable Multi-Core Real-Time Systems by SoC Co-Design. In 2021 IEEE 24th International Symposium on Real-Time Distributed Computing (ISORC 2021), pages 43–52, 2021. [ DOI ]
[9] Tobias Klaus, Matthias Becker, Wolfgang Schröder-Preikschat and Peter Ulbrich. Constrained Data-Age with Job-Level Dependencies: How to Reconcile Tight Bounds and Overheads. In 2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 66–79, 2021. [ DOI ]
[8] Christian Eichler, Henriette Hofmeier, Stefan Reif, Timo Hönig, Jörg Nolte and Wolfgang Schröder-Preikschat. Neverlast: An NVM-Centric Operating System for Persistent Edge Systems. In Proceedings of the 12th ACM SIGOPS Asia-Pacific Workshop on Systems, pages 146–153. Association for Computing Machinery, 2021. [ DOI ]
[7] Christian Eichler, Henriette Hofmeier, Stefan Reif, Timo Hönig, Jörg Nolte and Wolfgang Schröder-Preikschat. Neverlast: Towards the Design and Implementation of the NVM-based Everlasting Operating System. In Proceedings of the 54th Hawaii International Conference on System Sciences (HICSS-54), pages 7227–7236. ScholarSpace, 2021. [ DOI ]
[6] Stefan Reif, Benedict Herzog, Judith Hemp, Wolfgang Schröder-Preikschat and Timo Hönig. AI Waste Prevention: Time and Power Estimation for Edge Tensor Processing Units: Poster. In Proceedings of the Twelfth ACM International Conference on Future Energy Systems, pages 300–301. Association for Computing Machinery, 2021. [ DOI ]
[5] Benedict Herzog, Stefan Reif, Fabian Hügel, Timo Hönig and Wolfgang Schröder-Preikschat. Towards Automated System-Level Energy-Efficiency Optimisation Using Machine Learning: Poster. In Proceedings of the Twelfth ACM International Conference on Future Energy Systems, pages 274–275. Association for Computing Machinery, 2021. [ DOI ]
[4] Tobias Langer, Jonas Rabenstein, Timo Hönig and Wolfgang Schröder-Preikschat. No Coherence? No Problem! Virtual Shared Memory for MPSoCs. In 2021 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers (ROSS), pages 1–9, 2021. [ http ]
[3] Alexander Ludwig Pöppl. Evaluation of the Actor Model for the Parallelization of Block-Structured Adaptive HPC Applications. Dissertation, Technische Universität München, 2021.
[2] Fabian Lesniak, Fabian Kreß and Jürgen Becker. Transparent Near-Memory Computing with a Reconfigurable Processor. In Applied Reconfigurable Computing. Architectures, Tools, and Applications, pages 221–231. Springer International Publishing, 2021.
[1] Hassan Nassar, Hanna AlZughbi, Dennis Gnad, Lars Bauer, Mehdi Tahoori and Jörg Henkel. LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs. In International Conference on Computer-Aided Design (ICCAD), 2021.

2020

[58] Dominik Walter, Michael Witterauf and Jürgen Teich. Real-Time Scheduling of I/O Transfers for Massively Parallel Processor Arrays. In Proceedings of the 18th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), pages 1–11. IEEE, December 2020. [ DOI ]
[57] Marcel Mettler, Daniel Mueller-Gritschneder and Ulf Schlichtmann. A Distributed Hardware Monitoring System for Runtime Verification on Multi-tile MPSoCs. ACM Transactions on Architecture and Code Optimization (TACO), December 2020.
[56] N. Doan, A. Srivatsa, N. Fasfous, S. Nagel, T. Wild and A. Herkersdorf. On-Chip Democracy: A Study on the Use of Voting Systems for Computer Cache Memory Management. In 2020 IEEE International Conference on Industrial Engineering and Engineering Management (IEEM), December 2020.
[55] Alexandre Truppel, Tsun-Ming Tseng and Ulf Schlichtmann. PSION 2: Optimizing Physical Layout of Wavelength-Routed ONoCs for Laser Power Reduction. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2020.
[54] Martin Bogusz, Philipp Samfass, Alexander Pöppl, Jannis Klinkenberg and Michael Bader. Evaluation of Multiple HPC Parallelization Frameworks in a Shallow Water Proxy Application with Multi-Rate Local Time Stepping. In The 3rd Annual Parallel Applications Workshop, Alternatives To MPI+X. IEEE/ACM sigARCH, November 2020.
[53] M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leissa, Sebastian Hack, Jürgen Teich and Frank Hannig. AnyHLS: High-Level Synthesis with Partial Evaluation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 39(11):October 2020. [ DOI ]
[52] A. Srivatsa, S. Nagel, N. Fasfous, N. Doan, T. Wild and A. Herkersdorf. HyVE: A Hybrid Voting-based Eviction Policy for Caches. In 2020 IEEE Nordic Circuits and Systems Conference (NorCAS), October 2020.
[51] Martin Hecker. Timing Sensitive Dependency Analysis and its Application to Software Security. , Karlsruher Institut für Technologie, Fakultät für Informatik, 2020. [ DOI ]
[50] Marcel Brand, Michael Witterauf, Alberto Bosio and Jürgen Teich. Anytime Floating-Point Addition and Multiplication – Concepts and Implementations. In Proceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 157–164. IEEE, July 2020. [ DOI ]
[49] ######## Frank Hannig, Javier Navaridas, Dirk Koch and Ameer AbdelhadiProceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). [ DOI ]
[48] T. K. R. Arvind, Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig and Jürgen Teich. Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. In Proceedings of the 24th International Symposium on VLSI Design and Test (VDAT). IEEE, July 2020. [ DOI ]
[47] Jan Spieck, Stefan Wildermann and Jürgen Teich. Run-Time Scenario-Based MPSoC Mapping Reconfiguration Using Machine Learning Models. In 2019 ACM/IEEE 1st Workshop on Machine Learning for CAD (MLCAD), July 2020. [ DOI ]
[46] Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann and Jürgen Teich. A Bibliometric Approach for Detecting the Gender Gap in Computer Science. Communications of the ACM (CACM), 63(5):74–80, May 2020. [ DOI ]
[45] Christian Heidorn, Frank Hannig and Jürgen Teich. Design Space Exploration for Layer-parallel Execution of Convolutional Neural Networks on CGRAs. In Proceedings of the 23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 26–31. ACM, May 2020. [ DOI ]
[44] Stefan Reif, Benedict Herzog, Fabian Hügel, Timo Hönig and Wolfgang Schröder-Preikschat. Nearly Symmetric Multi-Core Processors. In 11th ACM SIGOPS Asia-Pacific Workshop on Systems (APSys'20), 2020.
[43] Mark Sagi, Nguyen Anh Vu Doan, Nael Fasfous, Thomas Wild and Andreas Herkersdorf. Fine-Grained Power Modeling of Multicore Processors Using FFNNs. In Embedded Computer Systems: Architectures, Modeling, and Simulation, pages 186–199. Springer International Publishing, 2020.
[42] M. Sagi, N. A. V. Doan, M. Rapp, T. Wild, J. Henkel and A. Herkersdorf. A Lightweight Nonlinear Methodology to Accurately Model Multi-Core Processor Power. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, :1-1, 2020. [ DOI ]
[41] Lin Chen, Franziska Eberle, Nicole Megow, Kevin Schewior and Clifford Stein. A general framework for handling commitment in online throughput maximization. Math. Program., 183(1):215–247, 2020. [ DOI ]
[40] Franziska Eberle, Nicole Megow and Kevin Schewior. Optimally Handling Commitment Issues in Online Throughput Maximization. In 28th Annual European Symposium on Algorithms, ESA 2020, September 7-9, 2020, Pisa, Italy (Virtual Conference), pages 41:1–41:15. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2020. [ DOI ]
[39] Furkan Turan and Ingrid Verbauwhede. Trust in FPGA-accelerated Cloud Computing. ACM Computing Surveys, 53(6):128:1-128:28, 2020.
[38] J. Spieck, S. Wildermann and J. Teich. Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs. In 2020 57th ACM/IEEE Design Automation Conference (DAC), pages 1-6, 2020. [ DOI ]
[37] Furkan Turan and Ingrid Verbauwhede. Proxy Re-Encryption for Accelerator Confidentiality in FPGA-Accelerated Cloud. Cryptology ePrint Archive, Report 2020/805 2020. \urlhttps://eprint.iacr.org/2020/805.
[36] Furkan Turan, Sujoy Sinha Roy and Ingrid Verbauwhede. HEAWS: An Accelerator for Homomorphic Encryption on the Amazon AWS FPGA. IEEE Transactions on Computers, 69(8):1185-1196, 2020.
[35] Sven Rheindt, Sebastian Maier, Nora Pohle, Lars Nolte, Oliver Lenke, Florian Schmaus, Thomas Wild, Wolfgang Schröder-Preikschat and Andreas Herkersdorf. DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based Architectures. International Journal of Parallel Programming, 2020. [ DOI ]
[34] Florian Schmaus, Sebastian Maier, Tobias Langer, Jonas Rabenstein, Timo Hönig, Lars Bauer, Jörg Henkel and Wolfgang Schröder-Preikschat. System Software for Resource Arbitration on Future Many-* Architectures. In 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pages 967-975. IEEE, 2020. [ DOI ]
[33] Grace Li Zhang, Michaela Brunner, Bing Li, Georg Sigl and Ulf Schlichtmann. Timing Resilience for Efficient and Secure Circuits. In Proceedings of the 25th Asia and South Pacific Design Automation Conference (ASP-DAC), January 2020. [ DOI ]
[32] Marcel Mettler, Daniel Mueller-Gritschneder and Ulf Schlichtmann. Runtime Monitoring of Inter- and Intra-Thread Requirements on Embedded MPSoCs. In Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems (VLSID), January 2020. [ DOI ]
[31] Alexandre Truppel, Tsun-Ming Tseng, Davide Bertozzi, José Carlos Alves and Ulf Schlichtmann. PSION+: Combining logical topology and physical layout optimization for Wavelength-Routed ONoCs. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.
[30] Jürgen Teich, Pouya Mahmoody, Behnaz Pourmohseni, Sascha Roloff, Wolfgang Schröder-Preikschat and Stefan Wildermann. Run-Time Enforcement of Non-functional Program Properties on MPSoCs. In A Journey of Embedded and Cyber-Physical Systems, pages 125–149. Springer, 2020. [ DOI ]
[29] Behnaz Pourmohseni, Michael Glaß, Jörg Henkel, Heba Khdr, Martin Rapp, Valentina Richthammer, Tobias Schwarzer, Fedor Smirnov, Jan Spieck, Jürgen Teich, Andreas Weichslgartner and Stefan Wildermann. Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future Perspective. Journal of Low Power Electronics and Applications, 10:1-37, 2020. [ DOI ]
[28] Marvin Damschen, Martin Rapp, Lars Bauer and Jörg Henkel. i-Core: A runtime-reconfigurable processor platform for cyber-physical systems. In Embedded, Cyber-Physical, and IoT Systems, 2020, Springer International Publishing, pages 1–36.
[27] Behnaz Pourmohseni. System-Level Mapping, Analysis, and Management of Real-Time Applications in Many-Core Systems. Ph.D. Forum at the Design, Automation and Test in Europe Conference (DATE). Ph.D. Forum Best Poster Award, 2020.
[26] Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann and Jürgen Teich. Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems. In Proceedings of the Workshop on Next Generation Real-Time Embedded Systems (NG-RES), pages 5:1–5:14, 2020. [ DOI ]
[25] Jürgen Teich, Behnaz Pourmohseni, Oliver Keszöcze, Jan Spieck and Stefan Wildermann. Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems. In Proceedings of the 25th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 629–636, January 2020. [ DOI ]
[24] Tobias Schwarzer. System-level Mapping of Dataflow Applications onto MPSoCs. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2020.
[23] Martin Rapp, Mark Sagi, Anuj Pathania, Andreas Herkersdorf and Jörg Henkel. Power- and Cache-Aware Task Mapping with Dynamic Power Budgeting for Many-Cores. IEEE Transactions on Computers, 69(1):1-13, 2020.
[22] Martin Rapp, Anuj Pathania, Tulika Mitra and Jörg Henkel. Neural Network-based Performance Prediction for Task Migration on S-NUCA Many-Cores. IEEE Transactions on Computers, 2020.
[21] Heba Khdr, Muhammad Shafique, Santiago Pagani, Andreas Herkersdorf and Jörg Henkel. Combinatorial Auctions for Temperature-Constrained Resource Management in Manycores. IEEE Transactions on Parallel and Distributed Systems, 31(7):1605–1620, 2020.
[20] Alberto Marchetti-Spaccamela, Nicole Megow, Jens Schlöter, Martin Skutella and Leen Stougie. On the Complexity of Conditional DAG Scheduling in Multiprocessor Systems. In Proceedings of the IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020.
[19] Bertrand Simon, Joachim Falk, Nicole Megow and Jürgen Teich. Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice. In Proceedings of the Workshop on Next Generation Real-Time Embedded Systems (NG-RES), pages 2:1–2:13, 2020. [ DOI ]
[18] Mohak Chadha, Jophin John and Michael Gerndt. Extending SLURM for Dynamic Resource-Aware Adaptive Batch Scheduling. In IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC) 2020, 2020. accepted for publication
[17] Xingfu Wu, Aniruddha Marathe, Siddhartha Jana, Ondrej Vysocky, Jophin John, Andrea Bartolini, Lubomir Riha, Michael Gerndt, Valerie Taylor and Sridutt Bhalachandra. Toward an End-to-End Auto-tuning Framework in HPC PowerStack. In Energy Efficient HPC State of Practice 2020, 2020. accepted for publication
[16] Antonios Antoniadis, Christian Coester, Marek Elias, Adam Polak and Bertrand Simon. Online metric algorithms with untrusted predictions. In Proceedings of the Thirty-Seventh International Conference on Machine Learning (ICML), 2020.
[15] Olivier Beaumont, Louis-Claude Canon, Lionel Eyraud-Dubois, Giorgio Lucarelli, Loris Marchal, Clément Mommessin, Bertrand Simon and Denis Trystram. Scheduling on Two Types of Resources: A Survey. ACM Computing Surveys, 2020.
[14] Vincent Fagnon, Imed Kacem, Giorgio Lucarelli and Bertrand Simon. Scheduling on Hybrid Platforms: Improved Approximability Window. In Proceedings of the Latin American Theoretical Informatics Symposium, 2020.
[13] Stefan Reif, Benedict Herzog, Judith Hemp, Timo Hönig and Wolfgang Schröder-Preikschat. Precious: Resource-Demand Estimation for Embedded Neural Network Accelerators. In Proceedings of the 1st International Workshop on Benchmarking Machine Learning Workloads on Emerging Hardware (CHALLENGE'20), 2020. [ http ]
[12] Tirthak Patel, Christopher Eibel, Thomas Zeiser, Devesh Tiwari, Adam Wagenhäuser and Timo Hönig. What does Power Consumption Behavior of HPC Jobs Reveal? In Proceedings of the 34th IEEE International Parallel and Distributed Processing Symposium (IPDPS'20), 2020. [ DOI ]
[11] Fabian Paus, Teng Huang and Tamim Asfour. Predicting Pushing Action Effects on Spatial Object Relations by Learning Internal Prediction Models. In IEEE International Conference on Robotics and Automation (ICRA), pages 10584–10590, 2020.
[10] Fabian Paus and Tamim Asfour. Probabilistic Representation of Objects and their Support Relations. In International Symposium on Experimental Robotics (ISER), 2020.
[9] Florian D. Loch, Martin Johns, Martin Hecker, Martin Mohr and Gregor Snelting. Hybrid Taint Analysis for Java EE. In Proceedings of the 35th Annual ACM Symposium on Applied Computing, pages 1716–1725. Association for Computing Machinery, 2020. [ DOI ] [ http ]
[8] Tanfer Alan, Andreas Gerstlauer and Jörg Henkel. Runtime accuracy-configurable approximate hardware synthesis using logic gating and relaxation. In Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1578–1581, 2020.
[7] Franziska Schirrmacher, Benedikt Lorch, Bernhard Stimpel, Thomas Köhler and Christian Riess. SR\(^\mbox2\): Super-Resolution With Structure-Aware Reconstruction. In IEEE International Conference on Image Processing, ICIP 2020, Abu Dhabi, United Arab Emirates, October 25-28, 2020, pages 533–537. IEEE, 2020. [ DOI ]
[6] Franziska Schirrmacher, Christian Riess and Thomas Köhler. Adaptive Quantile Sparse Image (AQuaSI) Prior for Inverse Imaging Problems. IEEE Trans. Computational Imaging, 6:503–517, 2020. [ DOI ]
[5] Paula Kaiser, Franziska Schirrmacher, Benedikt Lorch and Christian Riess. Learning to Decipher License Plates in Severely Degraded Images. In Pattern Recognition. ICPR International Workshops and Challenges - Virtual Event, January 10-15, 2021, Proceedings, Part VI, pages 544–559. Springer, 2020. [ DOI ]
[4] Christoph Erhardt. Operating-System Support for Efficient Fine-Grained Concurrency in Applications. Dissertation, Lehrstuhl für Verteilte Systeme und Betriebssysteme, Department Informatik, Friedrich-Alexander-Universität Erlangen-Nürnberg, 2020. [ http ]
[3] Sven Köhler, Benedict Herzog, Timo Hönig, Lukas Wenzel, Max Plauth, Jörg Nolte, Andreas Polze and Wolfgang Schröder-Preikschat. Pinpoint the Joules: Unifying Runtime-Support for Energy Measurements on Heterogeneous Systems. In 2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers (ROSS), pages 31–40, 2020. [ DOI ]
[2] Stefan Reif, Phillip Raffeck, Peter Ulbrich and Wolfgang Schröder-Preikschat. Control-Flow Migration for Data-Locality Optimisation in Multi-Core Real-Time Systems. In 2020 IEEE Real-Time Systems Symposium (RTSS), pages 371–374, 2020. [ DOI ]
[1] Luis Gerhorst, Stefan Reif, Benedict Herzog and Timo Hönig. EnergyBudgets: Integrating Physical Energy Measurement Devices into Systems Software. In 2020 Brazilian Symposium on Computing Systems Engineering (SBESC), pages 1-8, 2020. [ DOI ]

2019

[70] Marvin Damschen, Lars Bauer and Jörg Henkel. WCET Guarantees for Opportunistic Runtime Reconfiguration. In IEEE/ACM 38th International Conference on Computer-Aided Design (ICCAD), November 2019.
[69] Alexander Pöppl, Scott Baden and Michael Bader. A UPC++ Actor Library and Its Evaluation on a Shallow Water Proxy Application. In Parallel Applications Workshop, Alternatives To MPI+X. IEEE, November 2019.
[68] Andreas Herkersdorf. Tackling the MPSoC Data Locality Challenge with Regional Coherence and Near Memory Acceleration. Keynote talk, 2019 IEEE Nordic Circuits and Systems Conference (NorCAS), October 29, 2019.
[67] Ralph Palutke, Andreas Neubaum and Johannes Götzfried. SEVGuard: Protecting User Mode Applications using Secure Encrypted Virtualization. In SecureComm 2019 Proceedings. Springer, October 24, 2019.
[66] Mark Sagi, Nguyen Anh Vu Doan, Thomas Wild and Andreas Herkersdorf. Multicore Power Estimation using Independent Component Analysis based Modeling. In 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), October 2019.
[65] Wolfgang Schröder-Preikschat and Timo Hönig. Adaptive Memory Protection for Many-core Systems. Invited Talk University of Otago, New Zealand, October 4, 2019.
[64] Lars Bauer, Marvin Damschen, Dirk Ziegenbein, Arne Hamann, Alessandro Biondi, Giorgio Buttazzo and Jörg Henkel. Analyses and Architectures for Mixed-Critical Systems: Industry Trends and Research Perspective. In International Conference on Embedded Software (EMSOFT), pages 13:1–13:2, October 2019. Invited Special Session Extended Abstract
[63] Pieter Maene. Lightweight Roots of Trust for Modern Systems-on-Chip. Dissertation, Faculty of Engineering Science, KU Leuven, Belgium, 2019.
[62] Jan Spieck, Stefan Wildermann, Tobias Schwarzer, Jürgen Teich and Michael Glaß. Data-Driven Scenario-based Application Mapping for Heterogeneous Many-Core Systems. In Multicore/Many-core Systems-on-Chip (MCSoC 2019), pages 334–341, October 2019. [ DOI ]
[61] Michael Witterauf, Frank Hannig and Jürgen Teich. Polyhedral Fragments: An Efficient Representation for Symbolically Generating Code for Processor Arrays. In Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), pages 8:1–8:10. ACM, October 2019. [ DOI ]
[60] Wolfgang Schröder-Preikschat and Timo Hönig. Predictability Issues in Operating Systems: Time, Space, Energy. Invited Talk University of Wellington, New Zealand, September 23, 2019.
[59] Christian Heidorn, Michael Witterauf, Frank Hannig and Jürgen Teich. CNN-Inference on Coarse-Grained Reconfigurable Arrays under Throughput Constraints. Invited talk, 4th Tensilica Day – Trends in Modern Design of Configurable Processors, Leibnitz University Hannover, Germany, September 23, 2019.
[58] Wolfgang Schröder-Preikschat. Time predictability, energy awareness and security in embedded and real-time systems. Invited Talk University of Auckland, New Zealand, September 16, 2019.
[57] Jürgen Teich. Efficient Treatment of Uncertainty in System Reliability Analysis using Importance Measures. Invited Talk at the Workshop Intelligent Methods for Test and Reliability, Schloss Dagstuhl, September 12, 2019.
[56] Christian Heidorn, Michael Witterauf, Frank Hannig and Jürgen Teich. Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. Journal of Computers (JCP), 14(8):541–556, August 2019. [ DOI ]
[55] Faramarz Khosravi. System-Level Reliability Analysis and Optimization in the Presence of Uncertainty . Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2019.
[54] Alexandra Listl, Daniel Mueller-Gritschneder and Ulf Schlichtmann. MAGIC: A Wear-leveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs. In 2019 IEEE 17th International New Circuits and Systems Conference (NEWCAS), July 2019.
[53] Andreas Herkersdorf. As Embedded Systems Became Serious Grown-Ups, They Decide on Their Own. Invited Talk at the Workshop on Embedded Systems, Dedicated to Peter Marwedel on the Occasion of his 70th Birthday, Dortmund, July 4, 2019.
[52] Jürgen Teich. Run-Time Enforcement of Non-functional Program Properties on MPSoCs. Invited Talk at the Workshop on Embedded Systems, Dedicated to Peter Marwedel on the Occasion of his 70th Birthday, Dortmund, July 5, 2019.
[51] Tanja Harbaum. Dynamisch adaptive Mikroarchitekturen mit optimierten Speicherstrukturen und variablen Befehlssätzen. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2019.
[50] Ulf Schlichtmann and Li Zhang. Machine Learning Approaches for Efficient Design Space Exploration of Application-specific NoCs. Invited Talk at Xidian University, China, June 22, 2019.
[49] Volkmar Sieh, Robert Burlacu, Timo Hönig, Heiko Janker, Phillip Raffeck, Peter Wägemann and Wolfgang Schröder-Preikschat. Combining Automated Measurement-Based Cost Modeling With Static Worst-Case Execution-Time and Energy-Consumption Analyses. IEEE Embedded Systems Letters, 11(2):38–41, June 2019. [ DOI ]
[48] Wolfgang Schröder-Preikschat. Predictability Issues in Operating Systems. Keynote, International Conference on Architecture of Computing Systems (ARCS), Copenhagen, Denmark, May 23, 2019.
[47] Sascha Roloff, Frank Hannig and Jürgen Teich. Modeling and Simulation of Invasive Applications and Architectures. Springer, 2019. [ DOI ]
[46] Jürgen Teich. Multi-Core Computing with Timing, Reliability, and Security Guarantees. Invited Talk at The University of Tokyo, Japan, April 18, 2019.
[45] Marcel Brand, Michael Witterauf, Frank Hannig and Jürgen Teich. Anytime Instructions for Programmable Accuracy Floating-Point Arithmetic. In Proceedings of the ACM International Conference on Computing Frontiers (CF), pages 215–219. ACM, April 2019. [ DOI ]
[44] Alexandra Listl, Daniel Mueller-Gritschneder, Ulf Schlichtmann and Sani Nassif. SRAM Design Exploration with Integrated Application-Aware Aging Analysis. In Design, Automation, and Test in Europe (DATE), pages 1249-1252, March 2019.
[43] Tobias Schwarzer, Joachim Falk, Simone Müller, Martin Letras, Christian Heidorn, Stefan Wildermann and Jürgen Teich. Compilation of Dataflow Applications for Multi-Cores Using Adaptive Multi-Objective Optimization. ACM Transactions on Design Automation of Electronic Systems, 24(3):29:1–29:23, March 2019. [ DOI ]
[42] Marvin Damschen, Lars Bauer and Jörg Henkel. Worst-Case Execution Time Guarantees for Runtime-Reconfigurable Architectures. Ph.D. Forum at IEEE/ACM 22nd Design, Automation and Test in Europe Conference (DATE), March, 2019.
[41] Tobias Schwarzer. System-Level Mapping and Synthesis of Data Flow-Oriented Applications on MPSoCs. Ph.D. Forum at the Design, Automation and Test in Europe Conference (DATE). Ph.D. Forum Best Poster Award, March, 2019.
[40] Marcel Brand, Michael Witterauf, Éricles R. Sousa, Alexandru Tanase, Frank Hannig and Jürgen Teich. *-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing. Concurrency and Computation: Practice and Experience, February 2019. [ DOI ]
[39] S. Sinha Roy, F. Turan, K. Jarvinen, F. Vercauteren and I. Verbauwhede. FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data. In 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), pages 387-398, 2019.
[38] Daniel Mueller-Gritschneder. Advanced Virtual Prototyping and Communication Synthesis for Integrated System Design at Electronic System Level. Habilitation, Technical University of Munich, 2019.
[37] Furkan Turan and Ingrid Verbauwhede. Propagating Trusted Execution through Mutual Attestation. In 4th Workshop on System Software for Trusted Execution (SysTEX'19). ACM, 2019.
[36] Furkan Turan and Ingrid Verbauwhede. Compact and Flexible FPGA Implementation of Ed25519 and X25519. ACM Transactions on Embedded Computing Systems (TECS), 18(3):24, 2019.
[35] Sven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Thomas Wild and Andreas Herkersdorf. NEMESYS: Near-Memory Graph Copy Enhanced System-Software. In MEMSYS 19: The International Symposium on Memory Systems, 2019.
[34] Sven Rheindt, Sebastian Maier, Florian Schmaus, Thomas Wild, Wolfgang Schröder-Preikschat and Andreas Herkersdorf. SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore Architectures. In Proceedings of the 19th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pages 212–225. Springer, 2019. [ DOI ]
[33] Sebastian Maier, Timo Hönig, Peter Wägemann and Wolfgang Schröder-Preikschat. Asynchronous Abstract Machines: Anti-noise System Software for Many-core Processors. In Proceedings of the 9th International Workshop on Runtime and Operating Systems for Supercomputers (ROSS 2019), pages 19–26. ACM, 2019. [ DOI ] [ http ]
[32] Dirk Gabriel, Walter Stechele and Stefan Wildermann. Resource-Aware Parameter Tuning for Real-Time Applications. In Architecture of Computing Systems – ARCS 2019, pages 45–55. Springer International Publishing, 2019. [ DOI ]
[31] Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß and Jürgen Teich. Hard Real-Time Application Mapping Reconfiguration for NoC-Based Many-Core Systems. Real-Time Systems, 55(2):433–469, 2019. [ DOI ]
[30] Marvin Damschen. Worst-Case Execution Time Guarantees for Runtime-Reconfigurable Architectures. Dissertation, Chair of Embedded Systems (CES), Department of Informatics, Karlsruhe Institute of Technology, Germany, 2019.
[29] Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann and Jürgen Teich. Isola\-tion-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. In Proceedings of the 31th Euromicro Conference on Real-Time Systems (ECRTS 2019), pages 12:1–12:24, 2019. [ DOI ]
[28] Behnaz Pourmohseni, Fedor Smirnov, Heba Khdr, Stefan Wildermann, Jürgen Teich and Jörg Henkel. Thermally Composable Hybrid Application Mapping for Real-Time Applications in Heterogeneous Many-Core Systems. In Proceedings of the 40th IEEE Real-Time Systems Symposium (RTSS), 2019. [ DOI ]
[27] Akshay Srivatsa, Sven Rheindt, Dirk Gabriel, Thomas Wild and Andreas Herkersdorf. CoD: Coherence-on-Demand – Runtime Adaptable Working Set Coherence for DSM-Based Manycore Architectures. In Embedded Computer Systems: Architectures, Modeling, and Simulation, pages 18–33. Springer International Publishing, 2019.
[26] Anuj Pathania and Jörg Henkel. HotSniper: Sniper-Based Toolchain for Many-Core Thermal Simulations in Open Systems. Embedded Systems Letters (ESL), 2019.
[25] Heba Khdr, Hussam Amrouch and Jorg Henkel. Dynamic Guardband Selection: Thermal-Aware Optimization for Unreliable Multi-Core Systems. Transactions on Computers (TC), 2019.
[24] Nidhi Anantharajaiah, Fabian Kempf, Leonard Masing, Fabian Marc Lesniak and Juergen Becker. Dynamic and Scalable Runtime Block-based Multicast Routing for Networks on Chips. In Proceedings of the 12th International Workshop on Network on Chip Architectures, pages 10:1–10:6. ACM, 2019. [ DOI ]
[23] Isañas A. Comprés Ureña and Michael Gerndt. Towards Elastic Resource Management. In Tools for High Performance Computing 2017, pages 105–127. Springer International Publishing, 2019.
[22] Wolfgang Schröder-Preikschat. Adaptive Memory Protection for Many-Core Systems. Invited talk, ASECOLab Seminar, University of Hawaii at Manoa, January 4, 2019.
[21] Sami Salamin, Martin Rapp, Hussam Amrouch, Girish Pahwa, Yogesh Chauhan and Jörg Henkel. NCFET-Aware Voltage Scaling. In International Symposium on Low Power Electronics and Design (ISLPED), 2019.
[20] Jörg Henkel, Heba Khdr and Martin Rapp. Smart Thermal Management for Heterogeneous Multicores. In Design, Automation & Test in Europe (DATE), pages 132–137, 2019.
[19] Martin Rapp, Anuj Pathania, Tulika Mitra and Jörg Henkel. Prediction-Based Task Migration on S-NUCA Many-Cores. In Design, Automation & Test in Europe (DATE), pages 1579–1582, 2019.
[18] Leonard Masing, Fabian Lesniak and Jürgen Becker. Hybrid Prototyping for Manycore Design and Validation. In Applied Reconfigurable Computing, pages 319–333. Springer International Publishing, 2019.
[17] Martin Rapp, Sami Salamin, Hussam Amrouch, Girish Pahwa, Yogesh Chauhan and Jörg Henkel. Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores. In Design Automation Conference (DAC), pages 41, 2019.
[16] Jeeta Ann Chacko, Isañas Alberto Comprés Ureña and Michael Gerndt. Integration of Apache Spark with Invasive Resource Manager. In 2019 IEEE SmartWorld, Ubiquitous Intelligence and Computing, Advanced and Trusted Computing, Scalable Computing and Communications, Cloud and Big Data Computing, Internet of People and Smart City Innovation, 2019. Best Paper Award
[15] Mohak Chadha and Michael Gerndt. Modelling DVFS and UFS for Region-Based Energy Aware Tuning of HPC Applications. In IEEE International Parallel and Distributed Processing Symposium (IPDPS 2019), 2019.
[14] Felix Hundhausen, Denis Megerle and Tamim Asfour. Resource-Aware Object Classification and Segmentation for Semi-Autonomous Grasping with Prosthetic Hands. In IEEE/RAS International Conference on Humanoid Robots (Humanoids), pages 215–221, 2019.
[13] Martin Rapp, Hussam Amrouch, Marilyn Wolf and Jörg Henkel. Machine Learning Techniques to Support Many-Core Resource Management: Challenges and Opportunities. In 2019 ACM/IEEE 1st Workshop on Machine Learning for CAD (MLCAD), pages 1–6, 2019.
[12] Tobias Klaus, Peter Ulbrich, Phillip Raffeck, Benjamin Frank, Lisa Wernet, Maxim Ritter von Onciul and Wolfgang Schröder-Preikschat. Boosting Job-Level Migration by Static Analysis. In Proceedings of the 15th Annual Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2019), pages 17–22. TU Dresden & Leibniz Universität Hannover, 2019. [ http ]
[11] Bernhard Heinloth, Marco Ammon, Dustin Nguyen, Timo Hönig, Volkmar Sieh and Wolfgang Schröder-Preikschat. Cocoon: Custom-Fitted Kernel Compiled on Demand. In Proceedings of the 10th Workshop on Programming Languages and Operating Systems (PLOS '19), pages 1–7. ACM Digital Library, 2019. [ DOI ]
[10] Stefan Reif, Phillip Raffeck, Heiko Janker, Luis Gerhorst, Timo Hönig and Wolfgang Schröder-Preikschat. Earl: Energy-Aware Reconfigurable Locks. In Proceedings of the 9th Embedded Operating Systems Workshop (EWiLi 2019). ACM SIGBED Review, 2019. [ DOI ]
[9] Timo Hönig, Benedict Herzog and Wolfgang Schröder-Preikschat. Energy-Demand Estimation of Embedded Devices Using Deep Artificial Neural Networks. In Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing (SAC 2019), pages 617–624. ACM Digital Library, 2019. [ DOI ]
[8] Simon Schuster, Peter Wägemann, Peter Ulbrich and Wolfgang Schröder-Preikschat. Proving Real-Time Capability of Generic Operating Systems by System-Aware Timing Analysis. In Proceedings of the 25th Real-Time and Embedded Technology and Applications Symposium (RTAS 2019), pages 313–330. IEEE Computer Society, 2019. [ DOI ]
[7] Alexander Würstlein and Wolfgang Schröder-Preikschat. T-IBE-T: Identity-Based Encryption for Inter-Tile Communication. In Proceedings of the 12th European Workshop on Systems Security (EuroSec 2019), pages 1–6. ACM Digital Library, 2019. [ DOI ]
[6] Jian-Jia Chen, Tobias Hahn, Ruben Hoeksma, Nicole Megow and Georg von der Brüggen. Scheduling Self-Suspending Tasks: New and Old Results. In Proceedings of the 31st Euromicro Conference on Real-Time Systems (ECRTS 2019), 2019.
[5] Jophin John, Santiago Narvaez R and Michael Gerndt. Invasive Computing for Power Corridor Management. In Proceedings of the ParCo 2019: International Conference on Parallel Computing, 2019. accepted for publication
[4] Hussam Amrouch, Heba Khdr and Jörg Henkel. Aging Effects: From Physics to CAD. In Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms, 2019, Springer, pages 43–69.
[3] Ao Mo-Hellenbrand. Resource-Aware and Elastic Parallel Software Development for Distributed-Memory HPC Systems. Dissertation, Technische Universität München, 2019. [ http ]
[2] Franziska Eberle, Felix Fischer, Jannik Matuschke and Nicole Megow. On index policies for stochastic minsum scheduling. Operations Research Letters, 47(3):213–218, 2019.
[1] Phillip Raffeck, Peter Ulbrich and Wolfgang Schröder-Preikschat. Migration Hints in Real-Time Operating Systems. In 2019 IEEE Real-Time Systems Symposium (RTSS), pages 528–531, 2019. [ DOI ]

2018

[82] Daniel Krauß, Philipp Andelfinger, Fabian Paus, Nikolaus Vahrenkamp and Tamim Asfour. Evaluating and Optimizing Component-based Robot Architectures using Network Simulation. In Winter Simulation Conference, December 2018.
[81] Andreas Weichslgartner, Stefan Wildermann, Deepak Gangadharan, Michael Glaß and Jürgen Teich. A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. ACM Transactions on Embedded Computing Systems (TECS), 17(5):89:1–89:25, November 2018. [ DOI ]
[80] Jörg Henkel, Jürgen Teich, Stefan Wildermann and Hussam Amrouch. Dynamic Resource Management for Heterogeneous Many-Cores. In Proceedings of the International Conference on Computer-Aided Design (ICCAD), pages 60:1–60:6. ACM, November 2018. [ DOI ]
[79] Enrico Rossi, Marvin Damschen, Lars Bauer, Giorgio Buttazzo and Jörg Henkel. Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing with FPGAs. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 11(2):10:1–10:24, November 2018. [ DOI ]
[78] Benedic Herzog, Luis Gerhorst, Bernhard Heinloth, Stefan Reif, Timo Hönig and Wolfgang Schröder-Preikschat. INTSPECT: Interrupt Latencies in the Linux Kernel. In Proceedings of the 2018 Brazilian Symposium on Computing Systems Engineering (SBESC '18), pages 1–8, November 2018.
[77] Rainer Kartmann, Fabian Paus, Markus Grotz and Tamim Asfour. Extraction of Physically Plausible Support Relations to Predict and Validate Manipulation Action Effects. IEEE Robotics and Automation Letters (RA-L), 3(4):3991–3998, October 2018. [ DOI ]
[76] Timo Hönig. Exploiting Dynamic Electricity Prices with an Energy-Aware Runtime System for Heterogeneous HPC Clusters. Invited talk, Department of Computer Science, Reykjavík University (RU), Reykjavík, Iceland, October 2, 2018.
[75] Michael Witterauf and Jürgen Teich. Run-Time Requirement Enforcement for Loop Programs on Processor Arrays. In Proceedings of the 16th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), pages 1-11, October 2018. [ DOI ]
[74] Tobias Schwarzer, Sascha Roloff, Valentina Richthammer, Rami Khaldi, Stefan Wildermann, Michael Glaß and Jürgen Teich. On the Complexity of Mapping Feasibility in Many-Core Architectures. In Proceedings of Multicore/Many-core Systems-on-Chip (MCSoC-2018), September 2018.
[73] Leonard Masing, Akshay Srivatsa, Fabian Kreß, Nidhi Anantharajaiah, Andreas Herkersdorf and Jürgen Becker. In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures. In 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, September 2018. [ DOI ]
[72] Efstathios Sotiriou-Xanthopoulos, Leonard Masing, Sotirios Xydis, Kostas Siozios, Jürgen Becker and Dimitrios Soudris. OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures. ACM Trans. Embed. Comput. Syst., 17(5):86:1–86:27, September 2018. [ DOI ]
[71] Jürgen Teich. Run-Time Application Mapping in Many-Core Architectures. Invited Talk National University of Singapore, August 24, 2018.
[70] Jürgen Teich. Mixed Static/Dynamic Application Mapping for NoC-Based MPSoCs with Guarantees on Timing, Reliability and Security. Invited Talk Nanyang Technological University, Singapore, August 23, 2018.
[69] Wolfgang Schröder-Preikschat. Predictability Issues in Operating Systems. Invited talk, Federal University of Technology - Parana (UTFPR), Department of Computer Science, Curitiba, Brazil, August 7, 2018.
[68] Jürgen Teich. Hybrid Application Mapping for NoC-Based MPSoCs with Guarantees on Timing, Reliability and Security. Invited Talk University of New South Wales, Australia, July 31, 2018.
[67] Éricles R. Sousa. Memory and Interface Architectures for Invasive Tightly Coupled Processor Arrays. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2018.
[66] Sascha Roloff. Modeling and Simulation of Invasive Applications and Architectures. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2018.
[65] Jörg Henkel. Power Density and Circuit Aging – System-Level Means for Mitigation. Keynote, IEEE Computer Society Annual Symposium on VLSI, Hong Kong, July 10, 2018.
[64] Alexandra Listl, Daniel Mueller-Gritschneder, Fabian Kluge and Ulf Schlichtmann. Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping. In International On-Line Testing Symposium (IOLTS), July 2018.
[63] Éricles R. Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig and Jürgen Teich. Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. In Proceedings of the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, July 2018. [ DOI ]
[62] Oliver Reiche. A Domain-Specific Language Approach for Designing and Programming Heterogeneous Image Systems. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2018.
[61] Manuel Mohr. Aspects of Code Generation and Data Transfer Techniques for Modern Parallel Architectures. , Karlsruher Institut für Technologie, Fakultät für Informatik, 2018. [ DOI ]
[60] Peter Wägemann, Christian Dietrich, Tobias Distler, Peter Ulbrich and Wolfgang Schröder-Preikschat. Whole-System Worst-Case Energy-Consumption Analysis for Energy-Constrained Real-Time Systems. In Proceedings of the 30th Euromicro Conference on Real-Time Systems (ECRTS '18), pages 24:1–24:25, July 2018. [ DOI ]
[59] Christian Eichler, Tobias Distler, Peter Ulbrich, Peter Wägemann and Wolfgang Schröder-Preikschat. TASKers: A Whole-System Generator for Benchmarking Real-Time-System Analyses. In Proceedings of the 18th International Workshop on Worst-Case Execution Time Analysis (WCET 2018), pages 6:1–6:12, July 3, 2018. [ DOI ]
[58] Wolfgang Schröder-Preikschat. Predictability Issues in Operating Systems. Invited talk, Computer Science Colloquium, Leibniz Universität Hannover, June 29, 2018.
[57] Jürgen Teich. Methodologies for Application Mapping for NoC-Based MPSOCs. Keynote, Adaptive Many-Core Architectures and Systems workshop, York, UK, June 14, 2018.
[56] Timo Hönig, Christopher Eibel, Adam Wagenhäuser, Maximilian Wagner and Wolfgang Schröder-Preikschat. Making Profit with Albatross: A Runtime System for Heterogeneous High-Performance-Computing Clusters. In Proceedings of the 27th International Symposium on High-Performance Parallel and Distributed Computing (HPDC'18), pages 11–12. ACM, June 13, 2018. Poster session [ DOI ]
[55] Timo Hönig, Christopher Eibel, Adam Wagenhäuser, Maximilian Wagner and Wolfgang Schröder-Preikschat. How to Make Profit: Exploiting Fluctuating Electricity Prices with Albatross, A Runtime System for Heterogeneous HPC Clusters. In Proceedings of the 8th International Workshop on Runtime and Operating Systems for Supercomputers (ROSS 2018), pages Article No. 4. ACM, June 12, 2018. [ DOI ]
[54] Valentina Richthammer, Tobias Schwarzer, Stefan Wildermann, Jürgen Teich and Michael Glaß. Architecture Decomposition in System Synthesis of Heterogeneous Many-Core Systems. In 55th ACM/\allowbreak EDAC/\allowbreak IEEE Design Automation Conference (DAC 2018), June 2018.
[53] Christopher Eibel, Christian Gulden, Wolfgang Schröder-Preikschat and Tobias Distler. Strome: Energy-Aware Data-Stream Processing. In Proceedings of the 18th International Conference on Distributed Applications and Interoperable Systems (DAIS '18), pages 40–57. Springer, June 2018.
[52] Heba Khdr, Hussam Amrouch and Jörg Henkel. Aging-Constrained Performance Optimization for Multi Cores. In 55th ACM/EDAC/IEEE Design Automation Conference (DAC 2018), June 2018.
[51] Anuj Pathania, Heba Khdr, Muhammad Shafique, Tulika Mitra and Jörg Henkel. QoS-Aware Stochastic Power Management for Many-Cores. In 55th ACM/EDAC/IEEE Design Automation Conference (DAC 2018), June 2018.
[50] Timo Hönig. Linking Energy Awareness with Cost Effectiveness: Considering Fluctuating Electricity Prices for Operating Heterogeneous HPC Systems. Invited talk, Department of Computer Science, University of Texas at Austin (UT), Austin, TX, USA, June 1, 2018.
[49] Timo Hönig. Energy-Aware System Software for Operating Heterogeneous HPC Systems in the Age of Dynamic Electricity Pricing. Invited talk, Flux Research Group, School of Computing, University of Utah, Salt Lake City, UT, USA, June 5,, 2018. [ http ]
[48] Timo Hönig. Building a Runtime System for Heterogeneous HPC Clusters to Exploit Dynamic Electricity Pricing. Invited talk, Laboratory for Advanced System Software (LASS), College of Information and Computer Sciences, University of Massachusetts Amherst (UMass), Amherst, MA, USA, May 30,, 2018. [ http ]
[47] Bo Qiao, Oliver Reiche, Frank Hannig and Jürgen Teich. Automatic Kernel Fusion for Image Processing DSLs. In Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 76–85. ACM, May 2018. [ DOI ]
[46] Wolfgang Schröder-Preikschat. Adaptive Memory Protection for Many-Core Systems. Invited talk, Future Trends in SOC, Hasso-Plattner-Institut (HPI), Universität Potsdam, April 20, 2018.
[45] Christian Schmitt, Frank Hannig and Jürgen Teich. A Target Platform Description Language for Parallel Code Generation. In Workshop Proceedings of the 31st GI/ITG International Conference on Architecture of Computing Systems (ARCS), pages 59-66. VDE VERLAG GmbH, April 2018.
[44] Andreas Zwinkau. Resource-aware Programming in a High-level Language – Improved performance with manageable effort on clustered MPSoCs. , Karlsruher Institut für Technologie, Fakultät für Informatik, 2018. [ DOI ]
[43] Wolfgang Schröder-Preikschat. Predictability Issues in Operating Systems. Invited talk, NII Shonan Meeting on Resilient Machine-to-Machine Communication, Shonan Village, Japan, March 27, 2018.
[42] Stefan Reif and Wolfgang Schröder-Preikschat. Predictable Synchronisation Algorithms for Asynchronous Critical Sections. Technical Report CS-2018-03, Friedrich-Alexander-Universität Erlangen-Nürnberg, Department Informatik, 2018. [ DOI ]
[41] Jens Schedel. Funktional dedizierte Nutzung von Prozessorknoten zur Interferenzreduktion von Betriebssystemoperationen. Dissertation, Lehrstuhl für Verteilte Systeme und Betriebssysteme, Department Informatik, Friedrich-Alexander-Universität Erlangen-Nürnberg, 2018. [ http ]
[40] Wolfgang Schröder-Preikschat. Predictability Issues in Operating Systems. Invited talk, Federal University of Santa Catarina (UFSC), Software/Hardware Integration Lab (LISHA), Florianopolis, Brazil, February 28, 2018.
[39] Alexandru Tanase, Frank Hannig and Jürgen Teich. Symbolic Parallelization of Nested Loop Programs. Springer, 2018. [ DOI ]
[38] Tobias Schwarzer, Andreas Weichslgartner, Michael Glaß, Stefan Wildermann, Peter Brand and Jürgen Teich. Symmetry-eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(2):297-310, February 2018. [ DOI ]
[37] Stefan Reif and Wolfgang Schröder-Preikschat. A Predictable Synchronisation Algorithm. In Proceedings of the 23rd Annual Symposium on Principles and Practice of Parallel Programming (PPoPP '18), pages 415–416. ACM, February 2018. Poster session [ DOI ]
[36] Andreas Weichslgartner, Stefan Wildermann, Michael Glaß and Jürgen Teich. Invasive Computing for Mapping Parallel Programs to Many-Core Architectures. Springer, 2018. [ DOI ]
[35] Anuj Pathania. Scalable Task Schedulers for Many-Core Architectures. Dissertation, Chair of Embedded Systems, Department of Informatics, Karlsruhe Institute of Technology, Germany, 2018.
[34] Li Zhang. Advanced Timing for High-Performance Design and Security of Digital Circuits. Dissertation, Technical University of Munich, 2018.
[33] Grace Li Zhang, Bing Li, Yiyu Shi, Jiang Hu and Ulf Schlichtmann. EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration under Process Variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018.
[32] Dietmar Fey and Frank Hannig. Special Issue on Heterogeneous Real-Time Image Processing. Journal of Real-Time Image Processing, 14:513-515, 2018. [ DOI ]
[31] Tulika Mitra, Jürgen Teich and Lothar Thiele. Guest Editors’ Introduction: Special Issue on Time-Critical Systems Design. IEEE Design and Test of Computers, 35:5-7, 2018. [ DOI ]
[30] Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann and Jürgen Teich. The Gender Gap in Computer Science –- A Bibliometric Analysis. 2018. [ DOI ]
[29] Oliver Reiche, Mehmet Akif Özkan, Frank Hannig, Jürgen Teich and Moritz Schmid. Loop Parallelization Techniques for FPGA Accelerator Synthesis. Journal of Signal Processing Systems, 90:3-27, 2018. [ DOI ]
[28] Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi and Ulf Schlichtmann. Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018.
[27] Alexander Pöppl, Marvin Damschen, Florian Schmaus, Andreas Fried, Manuel Mohr, Matthias Blankertz, Lars Bauer, Jörg Henkel, Wolfgang Schröder-Preikschat and Michael Bader. Shallow Water Waves on a Deep Technology Stack: Accelerating a Finite Volume Tsunami Model using Reconfigurable Hardware in Invasive Computing. In Euro-Par 2017: Proceedings of the 10th Workshop on UnConventional High Performance Computing (UCHPC 2017), pages 676–687. Springer International Publishing, 2018.
[26] Johannes Götzfried. Trusted Systems in Untrusted Environments: Protecting against Strong Attackers. Dissertation, Chair for IT Security Infrastructures, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2018. [ http ]
[25] Sebastian Buchwald, Andreas Fried and Sebastian Hack. Synthesizing an Instruction Selection Rule Library from Semantic Specifications. In Proceedings of 2018 IEEE/ACM International Symposium on Code Generation and Optimization. ACM, 2018. [ DOI ]
[24] Simon Bischof, Joachim Breitner, Jürgen Graf, Martin Hecker, Martin Mohr and Gregor Snelting. Low-Deterministic Security For Low-Nondeterministic Programs. Journal of Computer Security, 26:335–366, 2018. [ DOI ]
[23] David Übler, Johannes Götzfried and Tilo Müller. Secure Remote Computation using Intel SGX. In Sicherheit 2018, Beiträge der 9. Jahrestagung des Fachbereichs Sicherheit der Gesellschaft für Informatik e.V. (GI), 25.-27.4.2018, Konstanz, pages 209–219. Gesellschaft für Informatik e.V., 2018. [ DOI ] [ http ]
[22] Ralph Palutke and Felix C. Freiling. Styx: Countering robust memory acquisition. Digital Investigation, 24:18–28, 2018. [ DOI ] [ http ]
[21] Johannes Götzfried. RAM-Schranke: RAM-Verschlüsselung bei AMD und Intel. c't Magazin für Computertechnik, 10:174–179, 2018. [ http ]
[20] Sven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild and Andreas Herkersdorf. CaCAO: Complex and Compositional Atomic Operations for NoC-based Manycore Platforms. In ARCS 2018 - 31st International Conference on Architecture of Computing Systems, 2018.
[19] Simon Schuster, Peter Wägemann, Peter Ulbrich and Wolfgang Schröder-Preikschat. Towards System-Wide Timing Analysis of Real-Time–Capable Operating Systems. In Proceedings of the 30th Euromicro Conference on Real-Time Systems (ECRTS '18), pages 10–12, 2018. [ http ]
[18] Peter Wägemann, Tobias Distler, Heiko Janker, Phillip Raffeck, Volkmar Sieh and Wolfgang Schröder-Preikschat. Operating Energy-Neutral Real-Time Systems. ACM Transactions on Embedded Computing Systems, 17(1):Article No. 11, January 2018. [ DOI ]
[17] Benjamin Oechslein. Leichtgewichtige Betriebssystemdienste für ressourcengewahre Anwendungen gekachelter Vielkernrechner. Dissertation, Lehrstuhl für Verteilte Systeme und Betriebssysteme, Department Informatik, Friedrich-Alexander-Universität Erlangen-Nürnberg, 2018. [ http ]
[16] Heba Khdr, Santiago Pagani, Muhammad Shafique and Jörg Henkel. Dark Silicon Aware Resource Management for Many-Core Systems. In Advances in Computers: Dark Silicon and Future of On-chip Systems, 2018, Elsevier,
[15] Heba Khdr, Hussam Amrouch and Jörg Henkel. Aging-Aware Boosting. IEEE Transactions on Computers (TC), 2018. [ DOI ]
[14] Anuj Pathania and Jörg Henkel. Task scheduling for many-cores with S-NUCA caches. In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 557–562, 2018.
[13] Vanchinathan Venkatramani, Anuj Pathania, Muhammad Shafique, Tulika Mitra and Jörg Henkel. Scalable Dynamic Task Scheduling on Adaptive Many-Core (invited). In 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2018.
[12] Martin Rapp, Anuj Pathania and Jörg Henkel. Pareto-Optimal Power- and Cache-Aware Task Mapping for Many-Cores with Distributed Shared Last-Level Cache. In International Symposium on Low Power Electronics and Design (ISLPED), 2018.
[11] Simon Bischof, Joachim Breitner, Denis Lohner and Gregor Snelting. Illi Isabellistes Se Custodes Egregios Praestabant. In Principled Software Development: Essays Dedicated to Arnd Poetzsch-Heffter on the Occasion of his 60th Birthday, 2018, Springer International Publishing, pages 267–282. [ DOI ] [ http ]
[10] Pieter Maene, Johannes Götzfried, Tilo Müller, Ruan de Clercq, Felix Freiling and Ingrid Verbauwhede. Atlas: Application Confidentiality in Compromised Embedded Systems. IEEE Transactions on Dependable and Secure Computing, 2018. [ DOI ]
[9] Vincent Lefebvre, Gianni Santinelli, Tilo Müller and Johannes Götzfried. Universal Trusted Execution Environments for Securing SDN/NFV Operations. In ARES 2018: International Conference on Availability, Reliability and Security. ACM, 2018. [ DOI ]
[8] Santiago Pagani, Sai Manoj PD, Axel Jantsch and Jörg Henkel. Machine Learning for Power, Energy, and Thermal Management on Multi-core Processors: A Survey. Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.
[7] Santiago Pagani, Jian-Jia Chen, Muhammad Shafique and Jörg Henkel. Advanced Techniques for Power, Energy, and Thermal Management for Clustered Manycores. Springer, 2018.
[6] Heba Khdr. Resource Management for Multicores to Optimize Performance under Temperature and Aging Constraints. Dissertation, Chair of Embedded Systems, Department of Informatics, Karlsruhe Institute of Technology, Germany, 2018.
[5] Pieter Maene, Johannes Götzfried, Ruan de Clercq, Tilo Müller, Felix Freiling and Ingrid Verbauwhede. Hardware-Based Trusted Computing Architectures for Isolation and Attestation. IEEE Transactions on Computers, 67(3):361-374, 2018. [ DOI ]
[4] Titouan Lazard, Johannes Götzfried, Tilo Müller, Gianni Santinelli and Vincent Lefebvre. TEEshift: Protecting Code Confidentiality by Selectively Shifting Functions into TEEs. In Proceedings of the 3rd Workshop on System Software for Trusted Execution, pages 14–19. ACM, 2018. [ DOI ] [ http ]
[3] Muhammad Aurang Zaib. Network on Chip Interface for Scalable Distributed Shared Memory Architectures. Dissertation, Technische Universität München, 2018.
[2] http ]
[1] Tanfer Alan and Jörg Henkel. Slackhammer: Logic synthesis for graceful errors under frequency scaling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(11):2802–2811, 2018.

2017

[74] Éricles Sousa, Alexandru Tanase, Frank Hannig and Jürgen Teich. A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE, December 2017. [ DOI ]
[73] Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig and Jürgen Teich. TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays. Demo Night at the International Conference on Reconfigurable Computing and FPGAs (ReConFig), December, 2017.
[72] Jürgen Teich. Application Mapping Methodologies for NoC-Based MPSoCs. Invited Talk University of California, Irvine, USA, November 14, 2017.
[71] Oliver Reiche, M. Akif Özkan, Richard Membarth, Jürgen Teich and Frank Hannig. Generating FPGA-based Image Processing Accelerators with Hipacc. In Proceedings of the International Conference On Computer Aided Design (ICCAD). IEEE, November 2017. Invited Paper
[70] Christian Eichler. Ein Benchmarkgenerator von WCET-Analysatoren. In Logik und Echtzeit, Echtzeit 2017, pages 59–68. Springer, Informatik aktuell, November 2017. [ DOI ]
[69] Sascha Roloff, Frank Hannig and Jürgen Teich. High Performance Network-on-Chip Simulation by Interval-based Timing Predictions. In Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia), pages 2–11. ACM, October 2017. [ DOI ]
[68] Michael Witterauf, Frank Hannig and Jürgen Teich. Constructing Fast and Cycle-Accurate Simulators for Configurable Accelerators Using C++ Templates. In Proceedings of the 28th International Symposium on Rapid System Prototyping (RSP), pages 9–15. ACM, October 2017. [ DOI ]
[67] Simon Schuster, Peter Ulbrich, Isabella Stilkerich, Christian Dietrich and Wolfgang Schröder-Preikschat. Demystifying Soft-Error Mitigation by Control-Flow Checking–-A New Perspective on its Effectiveness. In Proceedings of the 2017 International Conference on Embedded Software (EMSOFT 2017). ACM, October 2017. Poster session
[66] Simon Schuster, Peter Ulbrich, Isabella Stilkerich, Christian Dietrich and Wolfgang Schröder-Preikschat. Demystifying Soft-Error Mitigation by Control-Flow Checking–-A New Perspective on its Effectiveness. ACM Transactions on Embedded Computing Systems, 16(5s):Article No. 180, October 2017. Special Issue ESWEEK 2017, CASES 2017, CODES + ISSS 2017 and EMSOFT 2017 [ DOI ]
[65] Alexandru Tanase. Symbolic Parallelization of Nested Loop Programs. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2017.
[64] Marcel Brand, Frank Hannig, Alexandru Tanase and Jürgen Teich. Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. In Proceedings of the IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pages 5–12. IEEE Computer Society, September 2017. [ DOI ]
[63] Tanja Harbaum, Christoph Schade, Marvin Damschen, Carsten Tradowsky, Lars Bauer, Jörg Henkel and Jürgen Becker. Auto-SI: An Adaptive Reconfigurable Processor with Run-time Loop Detection and Acceleration. In 30th IEEE International System-on-Chip Conference (SOCC), pages 224–229. IEEE, September 2017. [ DOI ]
[62] Michael Glaß, Jürgen Teich, Martin Lukasiewycz and Felix Reimann. Hybrid Optimization Techniques for System-Level Design Space Exploration. In Handbook of Hardware/Software Codesign, 2017, Springer, pages 217–246. [ DOI ]
[61] Soonhoi Ha, Jürgen Teich, Christian Haubelt, Michael Glaß, Tulika Mitra, Rainer Dömer, Petru Eles, Aviral Shrivastava, Andreas Gerstlauer and Shuvra S. Bhattacharyya. Introduction to Hardware/Software Codesign. In Handbook of Hardware/Software Codesign, 2017, Springer, pages 3–26. [ DOI ]
[60] Joachim Falk, Christian Haubelt, Jürgen Teich and Christian Zebelein. SysteMoC: A Data-Flow Programming Language for Codesign. In Handbook of Hardware/Software Codesign, 2017, Springer, pages 59–97. [ DOI ]
[59] Santiago Pagani, Muhammad Shafique and Jörg Henkel. Design Space Exploration and Run-Time Adaptation for Multi-Core Resource Management Under Performance and Power Constraints. In Handbook of Hardware/Software Codesign, 2017, Springer, pages 301–332. [ DOI ]
[58] A. Srivatsa, S. Rheindt, T. Wild and A. Herkersdorf. Region Based Cache Coherence for Tiled MPSoCs. In 2017 30th IEEE International System-on-Chip Conference (SOCC), September 2017.
[57] Jürgen Teich. Application Mapping Methodologies for NoC-Based MPSoCs. Invited Talk University Lübeck, September 6, 2017.
[56] Jörg Henkel. The Triangle of Power Density, Circuit Degradation and Reliability. Invited Keynote Speech, 30th IEEE International System-On-Chip Conference (SoCC 2017), Munich, Germany, September 7, 2017.
[55] Johny Paul. Image Processing on Heterogeneous Multiprocessor System-on-Chip using Resource-aware Programming. Dissertation, Technische Universität München, 2017.
[54] Marcel Brand, Frank Hannig, Alexandru Tanase and Jürgen Teich. Efficiency in ILP Processing by Using Orthogonality. In Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 207. IEEE, July 2017. [ DOI ]
[53] Oliver Reiche, Christof Kobylko, Frank Hannig and Jürgen Teich. Auto-Vectorization for Image Processing DSLs. In Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded systems (LCTES). ACM, June 2017. [ DOI ]
[52] Stephanie Friederich. Automated Hardware Prototyping for 3D Networks on Chips. Dissertation, Institut für Technik der Informationsverarbeitung, Karlsruhe Institute of Technology (KIT), 2017.
[51] E. Glocker, Q. Chen, U. Schlichtmann and D. Schmitt-Landsiedel. Emulation of an ASIC power and temperature monitoring system (eTPMon) for FPGA prototyping. Microprocessors and Microsystems, 50:90-101, May 2017. [ DOI ]
[50] Lukas Meder. Timing Synchronization and Fast-Control for FPGA-based large-scale Readout and Processing Systems. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2017.
[49] Manuel Mohr and Carsten Tradowsky. Pegasus: Efficient Data Transfers for PGAS Languages on Non-Cache-Coherent Many-Cores. In Design, Automation and Test in Europe Conference Exhibition (DATE), pages 1781–1786, March 30, 2017.
[48] Hananeh Aliee. Reliability Analysis and Optimization of Embedded Systems using Stochastic Logic and Importance Measures. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2017.
[47] Marvin Damschen, Lars Bauer and Jörg Henkel. CoRQ: Enabling Runtime Reconfiguration under WCET Guarantees for Real-Time Systems. IEEE Embedded Systems Letters (ESL), 9(1):77-80, March 2017. [ DOI ]
[46] Heba Khdr, Santiago Pagani, Éricles R. Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich and Jörg Henkel. Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Transactions on Computers (TC), 66(3):488–501, March 1, 2017. [ DOI ]
[45] Anuj Pathania, Heba Khdr, Muhammad Shafique, Tulika Mitra and Jörg Henkel. Distributed scheduling for many-cores using cooperative game theory. In Design Automation and Test in Europe (DATE), March 2017.
[44] A. Pathania, V. Venkataramani, M. Shafique, T. Mitra and J. Henkel. Defragmentation of Tasks in Many-Core Architectures. ACM Transactions on Architecture and Code Optimization (TACO), 14(1):2:1–2:21, March 2017. [ DOI ]
[43] Artjom Grudnitsky, Lars Bauer and Jörg Henkel. Efficient Partial Online-Synthesis of Special Instructions for Reconfigurable Processors. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 25(2):594–607, February 2017. [ DOI ]
[42] Andreas Weichslgartner. Application Mapping Methodologies for Invasive NoC-Based Architectures. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2017.
[41] Rafael Rosales. Holistic Actor-oriented Modeling of Embedded Systems for ESL Power Consumption Evaluation. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2017.
[40] Jürgen Teich. Run-Time Monitoring and Enforcement of Non-functional Program Properties of Invasive Programs: Terms and Definitions. Technical Report, , 2017. [ http ]
[39] Jinglan Liu, Yukun Ding, Jianlei Yang, Ulf Schlichtmann and Yiyu Shi. Generative adversarial network based scalable on-chip noise sensor placement. In 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, pages 239–242, 2017. [ DOI ]
[38] Elisabeth Glocker. Thermisches Verhalten und emuliertes online Temperatur-Monitorsystem für das FPGA-Prototyping von Multiprozessor-Architekturen. Dissertation, Technical University of Munich, 2017.
[37] Isañas Alberto Comprés Ureña. Resource-Elasticity Support for Distributed Memory HPC Applications. Dissertation, Technical University of Munich, 2017. [ http ]
[36] Jürgen Teich. Run-Time Monitoring and Enforcement of Non-functional Program Properties of Invasive Programs: Terms and Definitions. Technical Report 01-2017, Hardware/Software Co-Design, Friedrich-Alexander-Universität Erlangen-Nürnberg, Department of Computer Science, 2017.
[35] David May. Automated Power Optimisation of Sequential Integrated Circuits Through Approximate Computing. Dissertation, Chair for Integrated Systems, Department of Electrical and Computer Engineering, Technische Universität München, Germany, 2017.
[34] Marvin Damschen, Lars Bauer and Jörg Henkel. Timing Analysis of Tasks on Runtime Reconfigurable Processors. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 25(1):294–307, January 2017. [ DOI ]
[33] Anatoli Kalysch, Johannes Götzfried and Tilo Müller. VMAttack: Deobfuscating Virtualization-Based Packed Binaries. In Proceedings of the 12th International Conference on Availability, Reliability and Security, pages 2:1–2:10. ACM, 2017. [ DOI ] [ http ]
[32] Job Noorman, Jo Van Bulck, Jan Tobias Mühlberg, Frank Piessens, Pieter Maene, Bart Preneel, Ingrid Verbauwhede, Johannes Götzfried, Tilo Müller and Felix C. Freiling. Sancus 2.0: A Low-Cost Security Architecture for IoT Devices. ACM Trans. Priv. Secur., 20(3):7:1–7:33, 2017. [ DOI ] [ http ]
[31] Pieter Maene, Johannes Götzfried, Ruan de Clercq, Tilo Müller, Felix Freiling and Ingrid Verbauwhede. Hardware-Based Trusted Computing Architectures for Isolation and Attestation. IEEE Transactions on Computers, 2017. In press. [ DOI ]
[30] Alexandru Tanase, Michael Witterauf, Jürgen Teich and Frank Hannig. Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Transactions on Embedded Computing Systems (TECS), 17(2):31:1–31:27, 2017. [ DOI ]
[29] Manuel Mohr and Carsten Tradowsky. Pegasus: Efficient Data Transfers for PGAS Languages on Non-Cache-Coherent Many-Cores. In Proceedings of Design, Automation and Test in Europe Conference Exhibition (DATE), pages 1781–1786. IEEE, 2017. [ DOI ]
[28] Santiago Pagani, Heba Khdr, Jian-Jia Chen, Muhammad Shafique, Minming Li and Jörg Henkel. Thermal Safe Power: Efficient Thermal-Aware Power Budgeting for Manycore Systems in Dark Silicon. In The Dark Side of Silicon, 2017, Springer,
[27] Santiago Pagani, Heba Khdr, Jian-Jia Chen, Muhammad Shafique, Minming Li and Jörg Henkel. Thermal Safe Power (TSP): Efficient Power Budgeting for Heterogeneous Manycore Systems in Dark Silicon. IEEE Transactions on Computers (TC), 66(1):147-162, 2017. \textbfFeature Paper of the Month [ DOI ]
[26] Santiago Pagani, Anuj Pathania, Muhammad Shafique, Jian-Jia Chen and Jörg Henkel. Energy Efficiency for Clustered Heterogeneous Multicores. IEEE Transactions on Parallel and Distributed Systems (TPDS), 28(5):1315-1330, 2017. [ DOI ]
[25] Christian Dietrich and Daniel Lohmann. OSEK-V: Application-Specific RTOS Instantiation in Hardware. In Proceedings of LCTES '17, 2017. [ DOI ] [ http ]
[24] Christian Dietrich, Peter Wägemann, Peter Ulbrich and Daniel Lohmann. SysWCET: Whole-System Response-Time Analysis for Fixed-Priority Real-Time Systems. In Proceedings of the 23rd Real-Time and Embedded Technology and Applications Symposium (RTAS '17), 2017. Outstanding Paper Award [ DOI ] [ http ]
[23] Christian Dietrich, Valentin Rothberg, Ludwig Füracker, Andreas Ziegler and Daniel Lohmann. cHash: Detection of Redundant Compilations via AST Hashing. In Proceedings of the 2017 USENIX Annual Technical Conference (ATC '17), pages 527–538, 2017. Best Paper Award [ http ]
[22] Ha, Soonhoi and Teich, Jürgen, editors. The Handbook of Hardware/Software Codesign. Springer, 2017. [ DOI ]
[21] Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß and Jürgen Teich. Predictable Run-Time Mapping Reconfiguration for Real-Time Applications on Many-Core Systems. In Proceedings of the International Conference on Real-Time Networks and Systems (RTNS). IEEE, 2017. Outstanding paper award [ DOI ]
[20] Behnaz Pourmohseni, Michael Glaß and Jürgen Teich. Automatic Operating Point Distillation for Hybrid Mapping Methodologies. In Proceedings of Design, Automation and Test in Europe Conference Exhibition (DATE), pages 1135-1140. IEEE, 2017. [ DOI ]
[19] Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker and Andreas Herkersdorf. Efficient Task Spawning for Shared Memory and Message Passing in Many-core Architectures. Journal of Systems Architecture (JSA), 2017. [ DOI ]
[18] Ruan de Clercq, Johannes Götzfried, David Übler, Pieter Maene and Ingrid Verbauwhede. SOFIA: Software and Control Flow Integrity Architecture. Computers & Security, 68:16-35, 2017. [ DOI ]
[17] Johannes Götzfried, Moritz Eckert, Sebastian Schinzel and Tilo Müller. Cache Attacks on Intel SGX. In Proceedings of the Tenth European Workshop on System Security (EuroSec'17), pages 2:1–2:6. ACM, 2017. [ DOI ] [ http ]
[16] Philipp Wagner, Thomas Wild and Andreas Herkersdorf. DiaSys: Improving SoC insight through on-chip diagnosis . Journal of Systems Architecture , 2017. [ DOI ]
[15] Ao Mo-Hellenbrand, Isañas Comprés, Oliver Meister, Hans-Joachim Bungartz, Michael Gerndt and Michael Bader. A Large-Scale Malleable Tsunami Simulation Realized on an Elastic MPI Infrastructure. In Proceedings of the Computing Frontiers Conference (CF), pages 271–274. ACM, 2017. [ DOI ]
[14] Stefan Reif, Timo Hönig and Wolfgang Schröder-Preikschat. In the Heat of Conflict: On the Synchronisation of Critical Sections. In Proceedings of the 20th IEEE Symposium on Real-Time Computing (ISORC 2017), pages 42–51. IEEE Computer Society Press, 2017. [ DOI ]
[13] Volkmar Sieh, Robert Burlacu, Timo Hönig, Heiko Janker, Phillip Raffeck, Peter Wägemann and Wolfgang Schröder-Preikschat. An End-To-End Toolchain: From Automated Cost Modeling to Static WCET and WCEC Analysis. In Proceedings of the 20th IEEE Symposium on Real-Time Computing (ISORC 2017), pages 158–167. IEEE Computer Society Press, 2017. [ DOI ]
[12] Peter Wägemann, Tobias Distler, Christian Eichler and Wolfgang Schröder-Preikschat. Benchmark Generation for Timing Analysis. In Proceedings of the 23rd IEEE International Symposium on Real-Time and Embedded Technology and Applications (RTAS '17), pages 319–330. IEEE Computer Society Press, 2017. [ DOI ]
[11] Christian Eichler, Peter Wägemann, Tobias Distler and Wolfgang Schröder-Preikschat. Tooling Support for Benchmarking Timing Analysis. In Proceedings of the 23rd IEEE International Symposium on Real-Time and Embedded Technology and Applications (RTAS Demo '17), pages 159–160. IEEE Computer Society Press, 2017. Demo Abstract
[10] Shushanik Karapetyan and Ulf Schlichtmann. 20nm FinFET-based SRAM Cell: Impact of Variability and Design Choices on Performance Characteristics. In Int. Conf. Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017.
[9] Mykola Protsenko. Securing the Android App Ecosystem: Obfuscation, Tamperproofing, and Malware detection. Dissertation, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2017.
[8] Ruzena Bajcsy, Yiannis Aloimonos and John K. Tsotsos. Revisiting active perception. Autonomous Robots, :1–20, 2017. [ DOI ]
[7] Markus Grotz, Timothee Habra, Renaud Ronsse and Tamim Asfour. Autonomous View Selection and Gaze Stabilization for Humanoid Robots. In 2017 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS). IEEE, 2017.
[6] Markus Grotz, Peter Kaiser, Eren Erdal Aksoy, Fabian Paus and Tamim Asfour. Graph-Based Visual Semantic Perception for Humanoid Robots. In 2017 IEEE-RAS 17th International Conference on Humanoid Robots (Humanoids). IEEE, 2017.
[5] Timothee Habra, Markus Grotz, David Sippel, Tamim Asfour and Renaud Ronsse. Multimodal Gaze Stabilization of a Humanoid Robot based on Reafferences. In 2017 IEEE-RAS 17th International Conference on Humanoid Robots (Humanoids). IEEE, 2017.
[4] Timo Hönig. Proactive Energy-Aware Computing. Dissertation, Friedrich-Alexander-Universität Erlangen-Nürnberg, 2017. [ http ]
[3] Fabian Paus, Peter Kaiser, Nikolaus Vahrenkamp and Tamim Asfour. A Combined Approach for Robot Placement and Coverage Path Planning for Mobile Manipulation. In IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), pages 6285–6292, 2017.
[2] Anuj Pathania, Heba Khdr, Muhammad Shafique, Tulika Mitra and Jörg Henkel. Scalable Probabilistic Power Budgeting for Many-Cores. In Proceedings of Design, Automation and Test in Europe Conference Exhibition (DATE). IEEE, 2017.
[1] Carsten Uphoff, Sebastian Rettenberger, Michael Bader, Stephanie Wollherr, Thomas Ulrich, Elizabeth H. Madden and Alice-Agnes Gabriel. Extreme Scale Multi-Physics Simulations of the Tsunamigenic 2004 Sumatra Megathrust Earthquake. In SC17: The International Conference for High Performance Computing, Networking, Storage and Analysis Proceedings, 2017. [ DOI ]

2016

[83] Carsten Tradowsky. Methoden zur applikationsspezifischen Effizienzsteigerung adaptiver Prozessorplattformen. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2016.
[82] Marvin Damschen, Lars Bauer and Jörg Henkel. Extending the WCET Problem to Optimize for Runtime-Reconfigurable Processors. ACM Transactions on Architecture and Code Optimization (TACO), 13(4):45:1–45:24, December 2016. [ DOI ]
[81] P. Wagner, L. Li, T. Wild, A. Mayer and A. Herkersdorf. What happens on an MPSoC stays on an MPSoC - unfortunately! In 2016 International Symposium on Integrated Circuits (ISIC), pages 1-2, December 2016. [ DOI ]
[80] Santiago Pagani. Power, Energy, and Thermal Management for Clustered Manycores. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2016. [ DOI ]
[79] Jürgen Teich. Invasive Computing – Editorial. it – Information Technology, 58(6):263–265, November 24, 2016. [ DOI ]
[78] Alexander Pöppl, Michael Bader, Tobias Schwarzer and Michael Glaß. SWE-X10: Simulating shallow water waves with lazy activation of patches using ActorX10. In Proceedings of the 2nd International Workshop on Extreme Scale Programming Models and Middleware (ESPM2), pages 32–39. IEEE, November 2016. [ http ]
[77] Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig, Jürgen Teich and Dibyendu Ghoshal. A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. Journal of Signal Processing Systems, 89(2):225–242, November 1, 2016. [ DOI ]
[76] Vahid Lari, Andreas Weichslgartner, Alex Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jürgen Becker, Jan Heißwolf and Stephanie Friederich. Providing Fault Tolerance Through Invasive Computing. it – Information Technology, 58(6):309–328, October 19 2016. [ DOI ]
[75] Hossein Tajik, Bryan Donyanavard, Nikil Dutt, Janmartin Jahn and Jörg Henkel. SPMPool: Runtime SPM Management for Memory-Intensive Applications in Embedded Many-Cores. ACM Trans. Embed. Comput. Syst., 16(1):25:1–25:27, October 2016. [ DOI ]
[74] Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner and Andreas Zwinkau. Invasive Computing for Timing-Predictable Stream Processing on MPSoCs. it – Information Technology, 58(6):267–280, September 30, 2016. [ DOI ]
[73] Gabor Drescher, Christoph Erhardt, Felix Freiling, Johannes Götzfried, Daniel Lohmann, Pieter Maene, Tilo Müller, Ingrid Verbauwhede, Andreas Weichslgartner and Stefan Wildermann. Providing Security on Demand Using Invasive Computing. it – Information Technology, 58(6):281–295, September 30 2016. [ DOI ]
[72] Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild and Jörg Henkel. Dark Silicon Management: An Integrated and Coordinated Cross-Layer Approach. it – Information Technology, 58(6):297–307, September 16, 2016. [ DOI ]
[71] Stephanie Friederich, Marco Neber and Jürgen Becker. Power Management Controller for Online Power Saving in Network-on-Chips. In International Symposium on Embedded Multicore/Manycore SoCs (MCSoC), September 2016.
[70] Jürgen Teich, Michael Glaß, Sascha Roloff, Wolfgang Schröder-Preikschat, Gregor Snelting, Andreas Weichslgartner and Stefan Wildermann. Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution using Invasive Computing. In Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pages 313-320, September 2016. [ DOI ]
[69] Anas Toma, Santiago Pagani, Jian-Jia Chen, Wolfgang Karl and Jörg Henkel. An Energy-Efficient Middleware for Computation Offloading in Real-Time Embedded Systems. In 22nd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), August 2016.
[68] Jürgen Teich. Predictability, Fault Tolerance, and Security on Demand using Invasive Computing. Invited Talk, University of Lübeck, Germany, July 29, 2016.
[67] Manfred Kröhnert. A Contribution to Resource-Aware Architectures for Humanoid Robots. Dissertation, High Performance Humanoid Technologies (H2T), KIT-Faculty of Informatics, Karlsruhe Institute of Technology (KIT), Germany, 2016.
[66] Michael Witterauf, Alexandru Tanase, Frank Hannig and Jürgen Teich. Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays. In Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 58–66. IEEE, July 2016. [ DOI ]
[65] Jürgen Teich. Invasive Computing - The DFG Transregional Research Center 89. DTC 2016, The Munich Workshop on Design Technology Coupling, Munich, Germany, June 30, 2016.
[64] Vahid Lari. Providing Fault Tolerance Through Invasive Computing. Talk at DTC 2016, The Munich Workshop on Design Technology Coupling, Munich, Germany, June 30, 2016.
[63] Mark Sagi and Andreas Herkersdorf. On-Chip Diagnosis of Multicore Platforms for Power Management. Workshop Presentation, DTC 2016, The Munich Workshop on Design Technology Coupling, Munich, Germany, June 30, 2016.
[62] Sascha Roloff, Alexander Pöppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Glaß, Frank Hannig and Jürgen Teich. ActorX10: An Actor Library for X10. In Proceedings of the 6th ACM SIGPLAN X10 Workshop (X10), pages 24–29. ACM, June 14, 2016. [ DOI ]
[61] Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra and Jörg Henkel. Distributed scheduling for many-cores using cooperative game theory. In Proceedings of the 53rd Annual Design Automation Conference (DAC), pages 133:1–133:6, June 2016.
[60] Ravi Kumar Pujari, Thomas Wild and Andreas Herkersdorf. TCU: A Multi-Objective Hardware Thread Mapping Unit for HPC Clusters. In High Performance Computing: 31st International Conference, ISC High Performance 2016, Frankfurt, Germany, June 19-23, 2016, Proceedings, pages 39-58. Springer International Publishing, June 2016. [ DOI ]
[59] Jürgen Teich. Predictable MPSoC Stream Processing Using Invasive Computing. Seminar Talk, Electrical and Computer Engineering, The University of Texas at Austin, USA, June 6, 2016.
[58] Andreas Weichslgartner, Stefan Wildermann, Johannes Götzfried, Felix Freiling, Michael Glaß and Jürgen Teich. Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs. In Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 153–162. ACM, May 23, 2016. [ DOI ]
[57] Manfred Kröhnert, Raphael Grimm, Nikolaus Vahrenkamp and Tamim Asfour. Resource-Aware Motion Planning. In IEEE International Conference on Robotics and Automation (ICRA), pages 32–39, May 2016. [ DOI ]
[56] Christopher Eibel, Timo Hönig and Wolfgang Schröder-Preikschat. Energy Claims at Scale: Decreasing the Energy Demand of HPC Workloads at OS Level. In IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pages 1114-1117, May 2016. [ DOI ]
[55] Fazal Hameed, Lars Bauer and Jörg Henkel. Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 35(4):651–664, April 2016.
[54] Jan Heisswolf, Stephanie Friederich, Leonard Masing, Aandreas Weichslgartner, Aurang M. Zaib, Carsten Stein, Marco Duden, Jürgen Teich, Thomas Wild, Andreas Herkersdorf and Jürgen Becker. A Novel NoC-Architecture for Fault Tolerance and Power Saving. In Proceedings of the third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, April 4, 2016.
[53] Andreas Weichslgartner and Jürgen Teich. Position Paper: Towards Redundant Communication through Hybrid Application Mapping. In Proceedings of the third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, April 4, 2016.
[52] Jürgen Teich. Adaptive Restriction and Isolation for Predictable MPSoC Stream Procesing. Invited Talk, DATE 2016 Friday Workshop on Resource Awareness and Application Autotuning in Adaptive and Heterogeneous Computing, Dresden, Germany, March 18, 2016.
[51] U. Schlichtmann. The next frontier in IC design: Determining (and optimizing) robustness and resilience of integrated circuits and systems. In 2016 China Semiconductor Technology International Conference (CSTIC), pages 1-4, March 2016. [ DOI ]
[50] Alexandru Tanase, Michael Witterauf, Éricles R. Sousa, Vahid Lari, Frank Hannig and Jürgen Teich. LoopInvader: A Compiler for Tightly Coupled Processor Arrays. Tool Presentation at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March, 2016. [ http ]
[49] Sascha Roloff, Frank Hannig and Jürgen Teich. InvadeSIM: A Simulator for Heterogeneous Multi-Processor Systems-on-Chip. Tool Presentation at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March, 2016. [ http ]
[48] Jörg Henkel, Santiago Pagani, Heba Khdr, Florian Kriebel, Semeen Rehman and Muhammad Shafique. Towards Performance and Reliability-Efficient Computing in the Dark Silicon Era. In Proceedings of the 19th Design, Automation and Test in Europe (DATE), March 2016.
[47] Shafaq Iqtedar, Osman Hasan, Muhammad Shafique and Jörg Henkel. Formal Probabilistic Analysis of Distributed Resource Management Schemes in On-Chip Systems. In IEEE/ACM 19th Design, Automation and Test in Europe Conference (DATE'16), pages 930–935, March 2016.
[46] Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra and Jörg Henkel. Distributed Fair Scheduling for Many-Cores. In Design Automation and Test in Europe (DATE), pages 379–384, March 2016.
[45] Jürgen Teich. Symbolic Loop Parallelization for Adaptive Multi-Core Systems - Recent Advances and Benefits. Keynote, IMPACT 2016, the 6th International Workshop on Polyhedral Compilation Techniques, 19 January, 2016, Prague, Czech Republic, January 19, 2016.
[44] Jürgen Teich. The Role of Restriction and Isolation for Increasing the Predictability of MPSoC Stream Processing. Keynote, 8th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO 2016), Prague, Czech Republic, January 18, 2016.
[43] Luca Fanucci and Jürgen Teich. Recap of the 2016 DATE Conference & Exhibition. IEEE Design & Test, 33(4):114–117, 2016. [ DOI ]
[42] Michael Feilen. Dynamic Partial Self-Reconfiguration of FPGAs for Digital Broadcasting Receiver Systems . Dissertation, Chair for Integrated Systems, Department of Electrical and Computer Engineering, Technische Universität München, Germany, 2016.
[41] Jürgen Graf. Information Flow Control with System Dependence Graphs – Improving Modularity, Scalability and Precision for Object Oriented Languages. Dissertation, Fakultät für Informatik, Karlsruher Institut für Technologie, Germany, 2016.
[40] Christian Herber. Enablement of Multicore-Based Automotive Embedded Systems through I/O and Network Virtualisation. Dissertation, Fakultät für Elektrotechnik und Informationstechnik, Technische Universität München, Germany, 2016.
[39] Sebastian Buchwald, Denis Lohner and Sebastian Ullrich. Verified Construction of Static Single Assignment Form. In 25th International Conference on Compiler Construction, pages 67–76. ACM, 2016. [ DOI ]
[38] Ruan de Clercq, Ronald de Keulenaer, Bart Coppens, Bohan Yang, Pieter Maene, Koen de Bosschere, Bart Preneel, Bjorn de Sutter and Ingrid Verbauwhede. SOFIA: Software and Control Flow Integrity Architecture. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE), pages 1172–1177. IEEE, 2016.
[37] Stephanie Friederich, Niclas Lehmann and Jürgen Becker. Adaptive Bandwidth Router for 3D Network-on-Chips. In Applied Reconfigurable Computing, pages 352–360, 2016. [ DOI ]
[36] Johannes Götzfried, Nico Dörr, Ralph Palutke and Tilo Müller. HyperCrypt: Hypervisor-based Encryption of Kernel and User Space. In 11th International Conference on Availability, Reliability and Security (ARES'16). IEEE, 2016. [ DOI ] [ http ]
[35] Lars Richter, Johannes Götzfried and Tilo Müller. Isolating Operating System Components with Intel SGX. In 1st Workshop on System Software for Trusted Execution (SysTEX'16). ACM, 2016. [ DOI ] [ http ]
[34] Johannes Götzfried, Tilo Müller, Gabor Drescher, Stefan Nürnberger and Michael Backes. RamCrypt: Kernel-based Address Space Encryption for User-mode Processes. In 11th ACM Asia Conference on Computer and Communications Security (ASAICCS). ACM, 2016. [ DOI ] [ http ]
[33] Furkan Turan, Ruan de Clercq, Pieter Maene, Oscar Reparaz and Ingrid Verbauwhede. Hardware Acceleration of a Software-based VPN. In 26th International Conference on Field Programmable Logic and Applications (FPL'16), pages 1-9. IEEE, 2016. [ DOI ]
[32] Hans Michael Gerndt, Michael Glaß, Sri Parameswaran and Barry L. Rountree. Dark Silicon: From Embedded to HPC Systems (Dagstuhl Seminar 16052). Dagstuhl Reports, 6(1):224–244, 2016. [ DOI ]
[31] Weifeng Liu, Michael Gerndt and Bin Gong. Model-based MPI-IO tuning with Periscope tuning framework. Concurrency and Computation: Practice and Experience, 28(1):3–20, 2016. [ DOI ]
[30] David May and Walter Stechele. Voltage over-scaling in sequential circuits for approximate computing. In 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pages 1–6, 2016.
[29] Alexander Pöppl and Alexander Herz. A cache-aware performance prediction framework for GPGPU computations. In Euro-Par 2015: Parallel Processing Workshops. Springer-Verlag, 2016.
[28] Alexander Pöppl and Michael Bader. SWE-X10: An Actor-based and Locally Coordinated Solver for the Shallow Water Equations. In Proceedings of the 6th ACM SIGPLAN Workshop on X10, pages 30–31. ACM, 2016. [ DOI ]
[27] Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang and Bing Li. Reliability, Adaptability and Flexibility in Timing: Buy a Life Insurance for Your Circuits. In IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pages 705-711. IEEE/ACM Press, January 2016. [ DOI ]
[26] A. K. Singh, M. Shafique, A. Kumar and J. Henkel. Resource and Throughput Aware Execution Trace Analysis for Efficient Run-time Mapping on MPSoCs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 35(1):72–85, January 2016. [ DOI ]
[25] Valentin Rothberg, Christian Dietrich, Alexander Graf and Daniel Lohmann. Function Multiverses for Dynamic Variability. In Proceedings of the 2016 IEEE International Workshops on Foundations and Applications of Self* Systems (FAS*W), pages 1–5, 2016. [ DOI ] [ http ]
[24] Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper and Jürgen Becker. A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems. Springer International Publishing, 2016. [ DOI ]
[23] Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper and Jürgen Becker. Adaptive Cache Structures. Springer International Publishing, 2016. [ DOI ]
[22] Carsten Tradowsky, Tanja Harbaum, Leonard Masing and Jürgen Becker. A Novel ADL-based Approach to Design Adaptive Application-Specific Processors. In Best of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016,
[21] Alexander Würstlein, Michael Gernoth, Johannes Götzfried and Tilo Müller. Exzess: Hardware-based RAM Encryption against Physical Memory Disclosure. In Architecture of Computing Systems (ARCS'16). Springer, 2016. [ DOI ] [ http ]
[20] Philipp Wagner, Thomas Wild and Andreas Herkersdorf. DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip. In Architecture of Computing Systems (ARCS'16). Springer, 2016.
[19] Grace Li Zhang, Bing Li and Ulf Schlichtmann. EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers. In Proceedings of the 53rd Annual Design Automation Conference (DAC), pages 60:1–60:6. ACM, 2016. [ DOI ]
[18] Andreas Zwinkau. A Memory Model for X10. In Proceedings of the 6th ACM SIGPLAN Workshop on X10, pages 7–12. ACM, 2016. [ DOI ]
[17] Vahid Lari. Invasive Tightly Coupled Processor Arrays. Springer Singapore, 2016. [ DOI ]
[16] Timo Hönig, Benedict Herzog and Wolfgang Schröder-Preikschat. The Narrow Way: Constructive Measures at Operating-System Level for Low Energy Use. In Proceedings of the 30th Environmental Informatics Conference (EnviroInfo 2016), pages 329-335, 2016.
[15] Mirko Wächter, Simon Ottenhaus, Manfred Kröhnert, Nikolaus Vahrenkamp and Tamim Asfour. The ArmarX Statechart Concept: Graphical Programming of Robot Behaviour. Frontiers in Robotics and AI, 3(33):2016. [ DOI ]
[14] A. Pathania, V. Venkataramani, M. Shafique, T. Mitra and J. Henkel. Optimal Greedy Algorithm for Many-Core Scheduling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), PP(99):1-1, 2016. [ DOI ]
[13] Isañas Comprés, Ao Mo-Hellenbrand, Michael Gerndt and Hans-Joachim Bungartz. Infrastructure and API Extensions for Elastic Execution of MPI Applications. In Proceedings of the 23rd European MPI Users' Group Meeting, pages 82–97. ACM, 2016. [ DOI ]
[12] Oliver Meister, Kaveh Rahnema and Michael Bader. Parallel Memory-Efficient Adaptive Mesh Refinement on Structured Triangular Meshes with Billions of Grid Cells. ACM Transactions on Mathematical Software, 43(3):19:1–19:27, 2016. [ DOI ]
[11] Oliver Meister. Sierpinski Curves for Parallel Adaptive Mesh Refinement in Finite Element and Finite Volume Methods. Dissertation, Technical University of Munich, 2016.
[10] Arash Bakhtiari, Dhairya Malhotra, Amir Raoofy, Miriam Mehl, Hans-Joachim Bungartz and George Biros. A Parallel Arbitrary-Order Accurate AMR Algorithm for the Scalar Advection-Diffusion Equation. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC). IEEE, 2016.
[9] Gabor Drescher and Wolfgang Schröder-Preikschat. Adaptive Memory Protection for Many-Core Systems. In Adaptive Isolation for Predictability and Security, 2016, Dagstuhl Publishing, pages 120–153:140. [ DOI ] [ http ]
[8] Tulika Mitra, Jürgen Teich and Lothar Thiele. Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441). Dagstuhl Reports, 6(10):120–153, 2016. [ DOI ]
[7] Tigist Abera, N. Asokan, Lucas Davi, Jan-Erik Ekberg, Thomas Nyman, Andrew Paverd, Ahmad-Reza Sadeghi and Gene Tsudik. C-FLAT: Control-Flow Attestation for Embedded Systems Software. In Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, pages 743–754. ACM, 2016.
[6] Michael Gruhn. Forensically Sound Data Acquisition in the Age of Anti-Forensic Innocence. Dissertation, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2016.
[5] Kristof Unterweger. High-performance Coupling of Dynamically Adaptive Grids and Hyperbolic Equation Systems. Dissertation, Technische Universität München, Fakultät für Informatik, 2016.
[4] Mirko Wächter, Simon Ottenhaus, Manfred Kröhnert, Nikolaus Vahrenkamp and Tamim Asfour. The ArmarX Statechart Concept: Graphical Programing of Robot Behavior. Frontiers in Robotics and AI, 3:33, 2016. [ DOI ]
[3] Peter Kaiser, Eren E. Aksoy, Markus Grotz and Tamim Asfour. Towards a Hierarchy of Loco-Manipulation Affordances. In IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), pages 2839–2846, 2016.
[2] Santiago Pagani, Heba Khdr, Jian-Jia Chen, Muhammad Shafique, Minming Li and Jörg Henkel. Thermal safe power (TSP): Efficient power budgeting for heterogeneous manycore systems in dark silicon. IEEE Transactions on Computers, 66(1):147–162, 2016.
[1] Heba Khdr, Santiago Pagani, Ericles Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich and Jörg Henkel. Power density-aware resource management for heterogeneous tiled multicores. IEEE Transactions on Computers, 66(3):488–501, 2016.

2015

[102] Artjom Grudnitsky. A Reconfigurable Processor for Heterogeneous Multi-Core Architectures. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2015.
[101] Muhammad Usman Karim Khan. Towards Computational Efficiency of Next Generation Multimedia Systems. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2015.
[100] Srinivas Boppu. Code Generation for Tightly Coupled Processor Arrays. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2015.
[99] Santiago Pagani, Jian-Jia Chen, Muhammad Shafique and Jörg Henkel. Thermal-Aware Power Budgeting for Dark Silicon Chips. In Proceedings of the 2nd Workshop on Low-Power Dependable Computing (LPDC) at the International Green and Sustainable Computing Conference (IGSC), December 2015.
[98] Oliver Reiche, Konrad Häublein, Marc Reichenbach, Moritz Schmid, Frank Hannig, Jürgen Teich and Dietmar Fey. Synthesis and optimization of image processing accelerators using domain knowledge. Journal of Systems Architecture (JSA), December 2015. [ DOI ]
[97] Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann and Jürgen Teich. The Gender Gap in Computer Science –- A Bibliometric Analysis. Technical Report 01-2015, Friedrich-Alexander University Erlangen-Nürnberg, Department of Computer Science, CRC/Transregio 89 Invasive Computing, 2015.
[96] Daniel Lohmann. Configurable System Software. Invited Talk, University of Ulm, November 28, 2015.
[95] Vahid Lari. Invasive Tightly Coupled Processor Arrays. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2015.
[94] Timo Hönig, Christopher Eibel, Benedict Herzog, Heiko Janker, Peter Wägemann and Wolfgang Schröder-Preikschat. Playing Hare and Tortoise: The FigarOS Kernel for Fine-Grained System-Level Energy Optimizations. In 2015 Brazilian Symposium on Computing Systems Engineering (SBESC '15). IEEE, November 2015. [ http ]
[93] Frank Hannig and Andreas Herkersdorf. Introduction to the Special Issue on Testing, Prototyping, and Debugging of Multi-Core Architectures. Journal of Systems Architecture, 61(10):600, November 7, 2015. [ DOI ]
[92] Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi and Brett H. Meyer. Techniques for On-Demand Structural Redundancy for Massively Parallel Processor Arrays. Journal of Systems Architecture (JSA), 61(10):615–627, November 2015. [ DOI ]
[91] Bing Li and U. Schlichtmann. Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 34(11):1784-1797, November 2015. [ DOI ]
[90] Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles R. Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer and Jörg Henkel. Resource-Awareness on Heterogeneous MPSoCs for Image Processing. Journal of Systems Architecture, 61(10):668–680, November 6, 2015. [ DOI ]
[89] M. Shafique and J. Henkel. Mitigating Power Density and Temperature Problems in the Nano-Era. In IEEE/ACM 34th International Conference on Computer-Aided Design (ICCAD), November 2, 2015. Special Session Paper
[88] Éricles R. Sousa, Frank Hannig and Jürgen Teich. Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays. In Proceedings of the International Embedded Systems Symposium (IESS). LNCS, November 2015.
[87] Stefan Wildermann. Time-predictable multi-core programming using Invasive Computing. Invited Talk at ESSEI TecDay: Multicore – The challenge in avionics, October 13, 2015.
[86] Lars Bauer, Artjom Grudnitsky, Marvin Damschen, Srinivas Rao Kerekare and Jörg Henkel. Floating Point Acceleration for Stream Processing Applications in Dynamically Reconfigurable Processors. In IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia), October 2015. Invited Paper for the Special Session ``Dynamics and Predictability in Stream Processing – A Contradiction?'' [ DOI ]
[85] Jörg Henkel. Dark Silicon and Dependability. Keynote Talk, International Symposium on Computer Architecture & Digital Systems (CADS), October 8, 2015.
[84] Santiago Pagani, Muhammad Shafique, Heba Khdr, Jian-Jia Chen and Jörg Henkel. seBoost: Selective Boosting for Heterogeneous Manycores. In 10th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 104–113, October 2015. [ DOI ]
[83] R. K. Pujari, T. Wild and A. Herkersdorf. A hardware-based multi-objective thread mapper for tiled manycore architectures. In Computer Design (ICCD), 2015 33rd IEEE International Conference on, pages 459–462, October 2015. [ DOI ]
[82] Sascha Roloff, Stefan Wildermann, Frank Hannig and Jürgen Teich. Invasive Computing for Predictable Stream Processing: A Simulation-based Case Study. In Proceedings of the 13th IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia). IEEE, October 2015. [ DOI ]
[81] Wolfgang Schröder-Preikschat. Predicatbility Issues in Operating Systems. Invited Talk, Technical University Dortmund, October 2, 2015.
[80] Daniel Lohmann. Predictability by Hardware-Centric Operating-System Design. Lecture, Sarntal Akademie, Italy, September 22, 2015.
[79] Wolfgang Schröder-Preikschat. Predicatbility in Operating Systems. Lecture, Sarntal Akademie, Italy, September 22, 2015.
[78] J. Henkel, H. Bukhari, S. Garg, M. U. K. Khan, H. Khdr, F. Kriebel, U. Ogras, S. Parameswaran and M. Shafique. Dark Silicon - From Computation to Communication. In International Symposium on Networks-on-Chip (NOCS), September 2015. Invited Special Session Paper
[77] Daniel Lohmann. Adaptable System Software. Invited Talk, Leibnitz-University Hanover, September 9, 2015.
[76] Santiago Pagani, Jian-Jia Chen and Jörg Henkel. Energy and Peak Power Efficiency Analysis for the Single Voltage Approximation (SVA) Scheme. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 34(9):1415-1428, September 2015. [ DOI ]
[75] Alexandru Tanase, Michael Witterauf, Jürgen Teich and Frank Hannig. Symbolic Loop Parallelization for Balancing I/O and Memory Accesses on Processor Arrays. In Proceedings of the 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), pages 188–197. IEEE, September 2015. [ DOI ]
[74] Michael Bader. Performance Optimzation vs. Power - Experiences with Petascale Earthquake Simulations on SuperMUC. Talk at the Workshop on Power-Bounded HPC Performance Optimisation at Schloss Dagstuhl, August, 2015.
[73] Sebastian Buchwald, Manuel Mohr and Ignaz Rutter. Optimal Shuffle Code with Permutation Instructions. In Algorithms and Data Structures, pages 528-541. Springer International Publishing, August 5, 2015. [ DOI ]
[72] Michael Dreschmann, Jan Heisswolf, Michael Geiger, Manuel Haußecker and Jürgen Becker. A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers. In Proceedings of the 28th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 5:1–5:6. ACM, August 2015. [ DOI ]
[71] Moritz Schmid. Rapid Prototyping for Hardware Accelerators in the Medical Imaging Domain. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2015.
[70] Andreas Herkersdorf. What happens on an MPSoC stays on an MPSoC \textendash unfortunately! Keynote Talk at MPSoC Forum, July 13, 2015.
[69] Alexander Breuer, Alexander Heinecke, Leonhard Rannabauer and Michael Bader. High-Order ADER-DG Minimizes Energy- and Time-to-Solution of SeisSol. In High Performance Computing, 30th International Conference, ISC High Performance 2015, Frankfurt, Germany, July 12-16, 2015, Proceedings, pages 340–357. Springer, July 2015.
[68] M. U. K. Khan, M. Shafique and J. Henkel. Hierarchical Power Budgeting for Dark Silicon Chips. In ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pages 213–218, July 2015. [ DOI ]
[67] A. Pathania, S. Pagani, M. Shafique and J. Henkel. Power Management for Mobile Games on Asymmetric Multi-Cores. In ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pages 243–248, July 2015. [ DOI ]
[66] Moritz Schmid, Oliver Reiche, Frank Hannig and Jürgen Teich. Loop Coarsening in C-based High-Level Synthesis. In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 166–173. IEEE, July 2015.
[65] Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig and Vahid Lari. On-Demand Fault-Tolerant Loop Processing on Massively Parallel Processor Arrays. In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 194–201. IEEE, July 2015. [ DOI ]
[64] Peter Wägemann, Tobias Distler, Timo Hönig, Heiko Janker, Rüdiger Kapitza and Wolfgang Schröder-Preikschat. Worst-Case Energy Consumption Analyis for Energy-Constrained Embedded Systems. In Proceedings of the 27th EUROMICRO Conference on Real-Time Systems (ECRTS 2015), pages 105–114, July 9, 2015. [ DOI ]
[63] Peter Wägemann, Tobias Distler, Timo Hönig, Volkmar Sieh and Wolfgang Schröder-Preikschat. GenE: A Benchmark Generator for WCET Analysis. In Proceedings of the 15th International Workshop on Worst-Case Execution Time Analysis (WCET 2015), pages 33–43, July 7 2015.
[62] Michael Witterauf, Alexandru Tanase, Frank Hannig and Jürgen Teich. Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing. In Proceedings of the 11th International Summer School on Advanced ComputerArchitecture and Compilation for High-Performance and Embedded Systems (ACACES), pages 205–208, July 2015.
[61] Manuel Mohr, Sebastian Buchwald, Andreas Zwinkau, Christoph Erhardt, Benjamin Oechslein, Jens Schedel and Daniel Lohmann. Cutting Out the Middleman: OS-Level Support for X10 Activities. In Proceedings of the fifth ACM SIGPLAN X10 Workshop, pages 13–18. ACM, June 14, 2015. [ DOI ]
[60] E. Glocker, Q. Chen, A.M. Zaidi, U. Schlichtmann and D. Schmitt-Landsiedel. Emulation of an ASIC power and temperature monitor system for FPGA prototyping. In Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015 10th International Symposium on, pages 1-8, June 2015. [ DOI ]
[59] D. Gnad, M. Shafique, F. Kriebel, S. Rehman, D. Sun and J. Henkel. Hayat: Harnessing Dark Silicon and Variability for Aging Deceleration and Balancing. In 52nd Design Automation Conference (DAC), pages 180:1–180:6, June 2015. \textbfHiPEAC Paper Award [ DOI ]
[58] Timo Hönig. Plan Ahead: Making Energy-Aware Computing Systems. Invited talk, ICSI, Berkeley, CA, USA, June 18, 2015.
[57] Timo Hönig. When Less is More: Invasive Energy Optimizations of System Software. Invited talk, University of California, Berkeley, CA, USA, June 11, 2015.
[56] Timo Hönig, Heiko Janker and Wolfgang Schröder-Preikschat. The FigarOS Operating System Kernel for Fine-Grained System-Level Energy Analysis. In DAC 2015 Workshop on System-to-Silicon Performance Modeling and Analysis: Power, Temperature and Reliability, June 7 2015.
[55] Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Stephanie Friederich, Leonard Masing, Carsten Stein, Marco Duden, Roman Klöpfer, Thomas Wild, Andreas Herkersdorf, Jürgen Teich and Jürgen Becker. Fault-tolerant Communication in Invasive Networks on Chip. In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pages 1–8. IEEE, June 2015.
[54] J. Henkel, H. Khdr, S. Pagani and M. Shafique. New Trends in Dark Silicon. In Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pages 119:1–119:6. ACM, June 2015. \textbfHiPEAC Paper Award [ DOI ]
[53] M. U. K. Khan, M. Shafique and J. Henkel. Hardware-Software Co-Design for Next Generation Dark Silicon Multimedia Systems. Ph.D. Forum at the ACM/EDAC/IEEE 52nd Design Automation Conference (DAC), June, 2015.
[52] H. Khdr, S. Pagani, M. Shafique and J. Henkel. Thermal Constrained Resource Management for Mixed ILP-TLP Workloads in Dark Silicon Chips. In 52nd Design Automation Conference (DAC), pages 179:1–179:6. ACM, June 2015. \textbfHiPEAC Paper Award [ DOI ]
[51] Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig and Brett H. Meyer. A Co-Design Approach for Fault-Tolerant Loop Execution on Coarse-Grained Reconfigurable Arrays. In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pages 1–8. IEEE, June 2015. [ DOI ]
[50] Santiago Pagani, Muhammad Shafique, Jian-Jia Chen and Jörg Henkel. Thermal-Aware Power Budgeting for Dark Silicon Chips (Invited talk). In Workshop on System-to-Silicon Performance Modeling and Analysis at the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), June 2015.
[49] Sascha Roloff, David Schafhauser, Frank Hannig and Jürgen Teich. Execution-driven Parallel Simulation of PGAS Applications on Heterogeneous Tiled Architectures. In Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pages 44:1–44:6. ACM, June 2015. [ DOI ]
[48] Éricles R. Sousa, Frank Hannig, Jürgen Teich, Qingqing Chen and Ulf Schlichtmann. Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. In Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 121–124. ACM, June 2015. [ DOI ]
[47] Jürgen Teich. Adaptive Isolation for Predictable MPSoC Stream Processing. Keynote, SCOPES 2015, 18th International Workshop on Software and Compilers for Embedded Systems, Schloss Rheinfels, St. Goar, Germany, June 2, 2015.
[46] Jürgen Teich. Adaptive Isolation for Predictable MPSoC Stream Processing. In Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2015), pages 1-2, June 2015. [ DOI ]
[45] Michael Witterauf, Alexandru Tanase, Jürgen Teich, Vahid Lari, Andreas Zwinkau and Gregor Snelting. Adaptive Fault Tolerance through Invasive Computing. In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pages 1–8. IEEE, June 2015. [ DOI ]
[44] Sebastian Kobbe. Scalable and Distributed Resource Management for Many-Core Systems. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2015.
[43] Jörg Henkel, Muhammad Usman Karim Khan and Muhammad Shafique. Energy-Efficient Multimedia Systems for High Efficiency Video Coding. In IEEE International Symposium on Circuits and Systems (ISCAS), May 2015. (accepted as a reviewed Special Session paper)
[42] Janmartin Jahn, Santiago Pagani, Sebastian Kobbe, Jian-Jia Chen and Jörg Henkel. Runtime Resource Allocation for Software Pipelines. ACM Transactions on Parallel Computing (TOPC), 2(1):5:1–5:23, May 2015. [ DOI ]
[41] Philipp Wagner, Lin Li, Thomas Wild, Albrecht Mayer and Andreas Herkersdorf. Knowledge-Based On-Chip Diagnosis for Multi-Core Systems-on-Chip. In edaWorkshop 15, pages 39–45, May 2015.
[40] Stefan Wildermann, Andreas Weichslgartner and Jürgen Teich. Design Methodology and Run-time Management for Predictable Many-Core Systems. In Proceedings of the 6th IEEE Workshop on Self-Organizing Real-Time Systems (SORT), pages 1–8, April 13 2015.
[39] Wolfgang Schröder-Preikschat. Invasive Computing: A Systems-Programming Perspective. Invited talk, Auckland University, Auckland, New Zealand, April 10, 2015.
[38] Sebastian Buchwald. Optgen: A Generator for Local Optimizations. In Proceedings of the International Conference on Compiler Construction (CC), pages 171–189. Springer Berlin Heidelberg, April 18, 2015. [ DOI ]
[37] Gabor Drescher and Wolfgang Schröder-Preikschat. Guarded Sections: Structuring Aid for Wait-Free Synchronisation. Poster at the 18th IEEE Symposium on Real-Time Computing (ISORC 2015). April 15, 2015.
[36] Preethi Parayil, Aurang Zaib, Thomas Wild, Stefan Wallentowitz and Andreas Herkersdorf. Sharer Status-based Caching in tiled Multiprocessor Systems-on-Chip. In HPC 2015 – 23rd High Performance Computing Symposia, pages 67–74. SCS, The Society for Modeling & Simulation, April 2015.
[35] Jürgen Teich, Srinivas Boppu, Frank Hannig and Vahid Lari. Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays. In Transforming Reconfigurable Systems: A Festschrift Celebrating the 60th Birthday of Professor Peter Cheung, 2015, Imperial College Press, pages 167–206. [ DOI ]
[34] Stefan Wildermann. Wieviele Prozessoren passen in eine Hosentasche? Invited Talk at Öffentliche Vortragsreihe Faszination Technik, April, 2015.
[33] Jürgen Teich. Invasive Computing. Invited Talk, SE 2015, Software Engineering and Management, Special Session Software Engineering in der DFG, Dresden, Germany, March 19, 2015.
[32] Michael Bader. Vectorization of Riemann Solvers for the Shallow Water Equations. Minisymposium Flooding the Cores - Computing Flooding Events with Many-Core and Accelerator Technologies at SIAM Conference on Computational Science and Engineering, March, 2015.
[31] Sebastian Buchwald, Manuel Mohr and Andreas Zwinkau. Malleable Invasive Applications. In Proceedings of the 8th Working Conference on Programming Languages (ATPS). Springer Berlin Heidelberg, March 18 2015.
[30] M. U. K. Khan, M. Shafique and J. Henkel. Hardware-Software Co-Design for Next Generation Dark Silicon Multimedia Systems. Ph.D. Forum at the IEEE/ACM 16th Design Automation and Test in Europe Conference (DATE). Ph.D. Forum Best Poster Award, March, 2015.
[29] Sebastian Kobbe, Lars Bauer and Jörg Henkel. Adaptive on-the-fly Application Performance Modeling for Many Cores. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 730–735, March 2015.
[28] Santiago Pagani, Jian-Jia Chen, Muhammad Shafique and Jörg Henkel. MatEx: Efficient Transient and Peak Temperature Computation for Compact Thermal Models. In 18th Design, Automation and Test in Europe (DATE), pages 1515–1520, March 2015. [ DOI ]
[27] Muhammad Shafique. Run-Time Resource and Reliability Management in Dark Silicon Many-Core Chips. Keynote Talk, International Workshop on Multi-Objective Many-Core Design (MOMAC), March, 2015.
[26] Muhammad Shafique, Dennis Gnad, Siddharth Garg and Jörg Henkel. Variability-Aware Dark Silicon Management in On-Chip Many-Core Systems. In 18th IEEE/ACM Design, Automation and Test in Europe (DATE), March 2015.
[25] Andreas Weichslgartner, Jan Heisswolf, Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jürgen Becker and Jürgen Teich. Position Paper: Towards Hardware-Assisted Decentralized Mapping of Applications for Heterogeneous NoC Architectures. In Proceedings of the second International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, March 2015.
[24] C. Diniz, M. Shafique, S. Bampi and J. Henkel. A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video Coding. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 34(2):February 2015.
[23] Fazal Hameed. DRAM aware Last-Level-Cache policies for Multi-core Systems. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2015.
[22] Daniel Lohmann. Two-Dimensional Tailoring of RTOS Kernels: Rethinking the Hardware–Application Bridge. Invited Talk, INRIA/LIP6 Paris, January 15, 2015.
[21] Alexander Breuer. High Performance Earthquake Simulations. Dissertation, Chair of Scientific Computing in Computer Science (SCCS), Technische Universität München, Germany, 2015.
[20] Maxim Anikeev, Felix Freiling, Johannes Götzfried and Tilo Müller. Secure garbage collection: Preventing malicious data harvesting from deallocated Java objects inside the Dalvik VM. In Journal of Information Security and Applications, pages 81–86. Elsevier, 2015. [ DOI ]
[19] Ruan De Clercq, Sujoy Sinha Roy, Ingrid Verbauwhede and Frederik Vercauteren. Efficient Software Implementation of Ring-LWE Encryption. In Design, Automation and Test in Europe (DATE 2015). IEEE, 2015.
[18] Gabor Drescher and Wolfgang Schröder-Preikschat. An Experiment in Wait-Free Synchronisation of Priority-Controlled Simultaneous Processes: Guarded Sections. Technical Report CS-2015-01, Friedrich-Alexander-Universität Erlangen-Nürnberg, Department of Computer Science, 2015.
[17] Gabor Drescher and Wolfgang Schröder-Preikschat. Wartefreie Synchronisation von Echtzeitprozessen mittels abgeschirmter Abschnitte. In Echtzeit 2015 –- Betriebssysteme und Echtzeit, pages 59–68. Springer, 2015.
[16] Gabor Drescher and Wolfgang Schröder-Preikschat. Guarded Sections: Structuring Aid for Wait-Free Synchronisation. In Proceedings of the 18th IEEE Symposium on Real-Time Computing (ISORC 2015), pages 280–283. IEEE Computer Society Press, 2015. [ DOI ]
[15] Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris and Jürgen Becker. A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware. In Applied Reconfigurable Computing, 2015, Springer International Publishing, pages 311-320.
[14] Johannes Götzfried, Tilo Müller, Ruan de Clercq, Pieter Maene, Felix Freiling and Ingrid Verbauwhede. Soteria: Offline Software Protection within Low-cost Embedded Devices. In Proceedings of the 31th Annual Computer Security Applications Conference (ACSAC'15), pages 241–250. ACM, 2015. [ DOI ] [ http ]
[13] Dennis Giffhorn and Gregor Snelting. A New Algorithm for Low-Deterministic Security. International Journal of Information Security, 14(3):263–287, 2015. [ DOI ]
[12] Christopher Kugler and Tilo Müller. Separated Control and Data Stacks to Mitigate Buffer Overflow Exploits. In Endorsed Transactions on Security and Safety, pages 1–36. European Alliance for Innovation (EAI), Institute for Computer Sciences, Social Informatics and Telecommunications Engineering (ICST), 2015.
[11] Andreas Lankes. A Selective Packet Discard Technique for Efficient Deadlock Recovery in Networks-on-Chip. Dissertation, Technische Universität München, Fakultät für Elektrotechnik und Informationstechnik, 2015.
[10] David May and Walter Stechele. Design of fine-grained sequential approximate circuits using probability-aware fault emulation. In Low Power Electronics and Design (ISLPED), 2015 IEEE/ACM International Symposium on, pages 73–78, 2015.
[9] Pieter Maene and Ingrid Verbauwhede. Single-Cycle Implementations of Block Ciphers. In Lightweight Cryptography for Security and Privacy. Springer-Verlag, 2015.
[8] Johny Paul, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Manfred Kröhnert, Daniel Lohmann, Walter Stechele, Tamim Asfour and Wolfgang Schröder-Preikschat. Self-adaptive corner detection on mpsoc through resource-aware programming. Journal of Systems Architecture, 2015. [ DOI ]
[7] Maximilian Seitzer, Michael Gruhn and Tilo Müller. A Bytecode Interpreter for Secure Program Execution in Untrusted Main Memory. In 20th European Symposium on Research in Computer Security (ESORICS'15), pages 376–395. SBA Research, 2015.
[6] Gregor Snelting. Understanding Probabilistic Software Leaks. Science of Computer Programming, 97, Part 1(0):122-126, January 2015. Special Issue on New Ideas and Emerging Results in Understanding Software [ DOI ]
[5] N. Vahrenkamp, M. Wächter, M. Kröhnert, K. Welke and T. Asfour. The Robot Software Framework ArmarX. Information Technology, 57(2):99–111, 2015.
[4] Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker and Andreas Herkersdorf. Network Interface with Task Spawning Support for NoC-based DSM Architectures. In 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS), pages 186–198. Springer, 2015. [ DOI ]
[3] Oliver Meister and Michael Bader. 2D adaptivity for 3D problems: Parallel SPE10 reservoir simulation on dynamically adaptive prism grids. Journal of Computational Science, 9:101–106, 2015. Special Issue ICCS 2015
[2] Peter Kaiser, Markus Grotz, Eren E. Aksoy, Martin Do, Nikolaus Vahrenkamp and Tamim Asfour. Validation of Whole-Body Loco-Manipulation Affordances for Pushability and Liftability. In IEEE/RAS International Conference on Humanoid Robots (Humanoids), pages 920–927, 2015.
[1] Heba Khdr, Santiago Pagani, Muhammad Shafique and Jörg Henkel. Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chips. In 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pages 1–6, 2015.

2014

[98] Waqaas Munawar, Heba Khdr, Santiago Pagani, Muhammad Shafique, Jian-Jia Chen and Jörg Henkel. Peak Power Management for Scheduling Real-time Tasks on Heterogeneous Many-Core Systems. In 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS), December 2014.
[97] Christoph Roth. Parallele und kooperative Simulation für eingebettete Multiprozessorsysteme. Dissertation, Institut für Technik der Informationsverarbeitung, Karlsruhe Institute of Technology (KIT), 2014. [ http ]
[96] M. Shafique and S. Rehman. Designing and Architecting Advanced Embedded Systems. Tutorial at National University of Sciences and Technology (NUST), December, 2014.
[95] Jürgen Teich. Reconfigurable Computing for MPSoC. Invited Lecture, Winter School Design and Applications of Multi Processor System on Chip, Tunis, Tunesia, November 26, 2014.
[94] Jan Heisswolf. A Scalable and Adaptive Network on Chip for Many-Core Architectures. Dissertation, Institut für Technik der Informationsverarbeitung, Karlsruhe Institute of Technology (KIT), 2014. [ http ]
[93] Deepak Gangadharan, Éricles Sousa, Vahid Lari, Frank Hannig and Jürgen Teich. Application-driven Reconfiguration of Shared Resources for Timing Predictability of MPSoC Platforms. In Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR), pages 398–403. IEEE, November 2014. [ DOI ]
[92] Felipe Sampaio, Muhammad Shafique, Bruno Zatt, Sergio Bampi and Jörg Henkel. Energy-Efficient Architecture for Advanced Video Memory. In IEEE/ACM 33rd International Conference on Computer-Aided Design (ICCAD), November 2014.
[91] Wolfgang Schröder-Preikschat. Invasive Computing: A Systems-Programming Perspective. Invited talk, TU Dresden, Institute of Systems Architecture, November 7, 2014.
[90] Muhammad Shafique. Application-Driven Power Management for On-Chip Memories. Invited Talk at Memory Architecture and Organization Workshop (MeAOW) at ESWeek, October 16,, 2014.
[89] Sebastian Graf, Felix Reimann, Michael Glaß and Jürgen Teich. Towards Scalable Symbolic Routing for Multi-Objective Networked Embedded System Design and Optimization. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014), pages 2:1–2:10, October 12, 2014. [ DOI ]
[88] Artjom Grudnitsky, Lars Bauer and Jörg Henkel. COREFAB: Concurrent Reconfigurable Fabric Utilization in Heterogeneous Multi-Core Systems. In International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), October 2014. [ DOI ]
[87] Timo Hönig, Heiko Janker, Oliver Mihelic, Christopher Eibel, Rüdiger Kapitza and Wolfgang Schröder-Preikschat. Proactive Energy-Aware Programming with PEEK. In 2014 Conference on Timely Results in Operating Systems (TRIOS '14). USENIX Association, October 2014. [ http ]
[86] Martin Haaß, Lars Bauer and Jörg Henkel. Automatic Custom Instruction Identification in Memory Streaming Algorithms. In International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), October 2014. [ DOI ]
[85] Jörg Henkel. Dependability of On-Chip Systems in the Dark Silicon Era. Keynote Talk, 32nd IEEE International Conference on Computer Design (ICCD), October, 2014.
[84] Jörg Henkel, Lars Bauer, Artjom Grudnitsky and Hongyan Zhang. Adaptive Embedded Computing with i-Core. In ACM SIGBED Review – Special Issue on the 6th Workshop on Adaptive and Reconfigurable Embedded Systems, pages 20–21, October 2014. Extended Abstract for Keynote Talk [ DOI ]
[83] Santiago Pagani, Heba Khdr, Waqaas Munawar, Jian-Jia Chen, Muhammad Shafique, Minming Li and Jörg Henkel. TSP: Thermal Safe Power - Efficient power budgeting for Many-Core Systems in Dark Silicon. In 9th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 10:1–10:10, October 2014. \textbfBest Paper Award [ DOI ]
[82] Johny Paul, Walter Stechele, Éricles R. Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert and Tamim Asfour. Self-Adaptive Harris Corner Detector on Heterogeneous Many-Core Processor. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP). IEEE, October 2014. [ DOI ]
[81] Muhammad Shafique, Siddharth Garg, Tulika Mitra, Sri Parameswaran and Jörg Henkel. Dark Silicon As a Challenge for Hardware/Software Co-design: Invited Special Session Paper. In IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2014. [ DOI ]
[80] Muhammad Shafique, Muhammad Usman Karim Khan and Jörg Henkel. Power Efficient and Workload Balanced Tiling for Parallelized High Efficiency Video Coding. In 21st IEEE International Conference on Image Processing (ICIP), October 2014.
[79] Isabella Stilkerich, Michael Strotz, Christoph Erhardt and Michael Stilkerich. RT-LAGC: Fragmentation-Tolerant Real-Time Memory Management Revisited. In Proceedings of the 12th International Workshop on Java Technologies for Real-time and Embedded Systems (JTRES '14), pages 87–96. ACM, October 14, 2014. [ DOI ]
[78] Isabella Stilkerich, Philip Taffner, Christoph Erhardt, Christian Dietrich, Christian Wawersich and Michael Stilkerich. Team Up: Cooperative Memory Management in Embedded Systems. In Proceedings of the 2014 Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES'14), pages Art. No. 10. ACM, October 13, 2014. [ DOI ]
[77] Alexandru Tanase, Michael Witterauf, Jürgen Teich and Frank Hannig. Symbolic Inner Loop Parallelisation for Massively Parallel Processor Arrays. In Proceedings of the 12th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), pages 219–228, October 2014. [ DOI ]
[76] Jürgen Teich. Invasive Computing – Concepts and Benefits. Keynote, DASIP 2014, Conference on Design and Architectures for Signal and Image Processing, Madrid, Spain, October 8, 2014.
[75] Peter Wägemann, Timo Hönig, Rüdiger Kapitza and Wolfgang Schröder-Preikschat. Worst-Case Energy Consumption Analysis for Soft and Hard Energy Systems. 11th USENIX Symposium on Operating System Design and Implementation (OSDI '14) October 2014. Poster.
[74] Andreas Weichslgartner, Deepak Gangadharan, Stefan Wildermann, Michael Glaß and Jürgen Teich. DAARM: Design-Time Application Analysis and Run-Time Mapping for Predictable Execution in Many-Core Systems. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014), pages 1–10, October 2014. [ DOI ]
[73] Jürgen Teich. System-Level Design Automation of Embedded Systems. Invited Talk, Tagung Deutsche Forschungsgesellschaft für Automatisierung und Mikroelektronik e.V. (DFAM), September 25, 2014.
[72] Stephanie Friederich, Jan Heisswolf and Jürgen Becker. Hardware/software debugging of large scale many-core architectures. In Proceedings of the 27th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 1–7. IEEE, September 2014. [ DOI ]
[71] Martin Schreiber, Christoph Riesinger, Tobias Neckel, Hans-Joachim Bungartz and Alexander Breuer. Invasive Compute Balancing for Applications with Shared and Hybrid Parallelization. International Journal of Parallel Programming, September 2014. [ DOI ]
[70] Tobias Weinzierl, Michael Bader, Kristof Unterweger and Roland Wittmann. Block Fusion on Dynamically Adaptive Spacetree Grids for Shallow Water Waves. Parallel Processing Letters, 24(3):1441006, September 2014.
[69] Stefan Nürnberger, Gabor Drescher, Randolf Rotta, Jörg Nolte and Wolfgang Schröder-Preikschat. Shared Memory in the Many-Core Age. In Proceedings of the International Workshop on Runtime and Operating Systems for the Many-core Era (ROME 2014). Springer, August 26, 2014.
[68] Felipe Sampaio, Muhammad Shafique, Bruno Zatt, Sergio Bampi and Jörg Henkel. Content-Driven Memory Pressure Balancing and Video Memory Power Management for Parallel High Efficiency Video Coding. In ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), August 2014. [ DOI ]
[67] Éricles Sousa, Deepak Gangadharan, Frank Hannig and Jürgen Teich. Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures. In Proceedings of the EUROMICRO Digital System Design Conference (DSD), pages 74–81. IEEE, August 2014. [ DOI ]
[66] Jürgen Teich. Foundations and Benefits of Invasive Computing. Seminar, Mc Gill University, Montreal, July 29, 2014.
[65] Jürgen Teich, Alexandru Tanase and Frank Hannig. Symbolic Mapping of Loop Programs onto Processor Arrays. Journal of Signal Processing Systems, 77(1–2):31–59, July 11, 2014. [ DOI ]
[64] Daniel Lohmann. Automatic Tailoring of System Software: Rethinking the Application-Hardware Bridge. Invited talk June 23, 2014. D. E. Shaw Research, New York City, USA.
[63] R. de Clercq, F. Piessens, D. Schellekens and I. Verbauwhede. Secure Interrupts on Low-End Microcontrollers. In IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 147–152, June 2014. [ DOI ]
[62] Fazal Hameed, Lars Bauer and Jörg Henkel. Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture. In IEEE/ACM Design Automation Conference (DAC), June 2014. [ DOI ]
[61] M. U. K. Khan, M. Shafique and J. Henkel. Application-Specific Hierarchical Power Management for Multicast High Efficiency Video Coding. In ACM/EDAC/IEEE 51st Design Automation Conference (DAC), June 2014. Designer Track Best Poster Award
[60] Muhammad Shafique, Siddharth Garg, Jörg Henkel and Diana Marculescu. The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives. In 51st Design Automation Conference (DAC), June 2014. [ DOI ]
[59] Srinivas Boppu, Frank Hannig and Jürgen Teich. Compact Code Generation for Tightly-Coupled Processor Arrays. Journal of Signal Processing Systems, 77(1–2):5–29, May 31, 2014. [ DOI ]
[58] Jürgen Teich. Introduction to Invasive Computing. Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), Paderborn, Germany, Tutorial Talk, May 29, 2014.
[57] Jürgen Teich. Foundations and Benefits of Invasive Computing. University of Bologna, Italy, Invited Talk in the Seminar Series Trends in Electronics, May 23, 2014.
[56] Michael Glaß, Michael Bader, Jürgen Teich and Stefan Wildermann. Assisting Run-time Optimization of Many-Core Systems by Design-time Characterization. HiPEAC Spring Computing Systems Week, Barcelona, Invited Talk, May 13, 2014.
[55] Jörg Henkel. The Dark Silicon Problem in Multi-Core Systems – Invasive Computing as a Solution. Keynote Talk, Thematic Session at HiPEAC Computer Systems Week, May 13,, 2014.
[54] Elisabeth Glocker, Qingqing Chen, Asheque M. Zaidi, Ulf Schlichtmann and Doris Schmitt-Landsiedel. Emulated ASIC Power and Temperature Monitor System for FPGA Prototyping of an Invasive MPSoC Computing Architecture. In Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), pages 14–15, May 2014.
[53] Manfred Kröhnert, Nikolaus Vahrenkamp, Johny Paul, Walter Stechele and Tamim Asfour. Resource Prediction for Humanoid Robots. In Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), pages 22–28, May 2014.
[52] Vahid Lari, Alexandru Tanase, Frank Hannig and Jürgen Teich. Massively Parallel Processor Architectures for Resource-aware Computing. In Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), pages 1–7, May 2014.
[51] Aurang Zaib, Prashanth Raju, Thomas Wild and Andreas Herkersdorf. A Layered Modeling and Simulation Approach to investigate Resource-aware Computing in MPSoCs. In Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), pages 51–56, May 2014.
[50] Hannig, Frank and Teich, Jürgen, editors. Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014). , 2014.
[49] Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann and Wolfgang Schröder-Preikschat. OctoPOS: A Hardware-Assisted OS for Many-Cores. Poster presentation at the 9th European Conference on Computer Systems (EuroSys 2014) April 15, 2014.
[48] Jörg Henkel. Adaptive Embedded Computing with i-Core. Keynote Talk, 6th Workshop on Adaptive and Reconfigurable Embedded Systems, CPSWeek (APRES), April 14,, 2014.
[47] Carsten Tradowsky, Martin Schreiber, Malte Vesper, Ivan Domladovec, Maximilian Braun, Hans-Joachim Bungartz and Jürgen Becker. Towards Dynamic Cache and Bandwidth Invasion. In Reconfigurable Computing: Architectures, Tools, and Applications, 2014, Springer International Publishing, pages 97–107. [ DOI ]
[46] Deepak Gangadharan, Alexandru Tanase, Frank Hannig and Jürgen Teich. Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays. In DATE Friday Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES). ECSI, March 28, 2014. [ http ]
[45] Alcides Fonseca, Paulo Marques and Jonathan Aldrich. AEminium: A Permission Based Concurrent-by-Default Programming Language Approach. ACM Transactions on Programming Languages and Systems, 36(1):2:1–2:42, March 2014. [ DOI ]
[44] Muhammad Usman Karim Khan, Muhammad Shafique and Jörg Henkel. Software Architecture of High Efficiency Video Coding for Many-core Systems with Power-efficient Workload Balancing. In Design, Automation and Test in Europe (DATE), March 2014. [ DOI ]
[43] F. Sampaio, M. Shafique, B. Zatt, S. Bampi and J. Henkel. dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding. In Design, Automation and Test in Europe (DATE), March 2014. [ DOI ]
[42] Wolfgang Schröder-Preikschat. Embedded Computing Systems in the Multi-Core Era. Invited talk, University of Canterbury, Christchurch, New Zealand, March 7, 2014.
[41] Éricles Sousa, Vahid Lari, Johny Paul, Frank Hannig, Jürgen Teich and Walter Stechele. Resource-Aware Computer Vision Application on Heterogeneous Multi-Tile Architecture. Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March, 2014.
[40] Stefan Wildermann, Michael Glaß and Jürgen Teich. Multi-Objective Distributed Run-time Resource Management for Many-Cores. In Proceedings of Design, Automation and Test in Europe (DATE), pages 1-6, March 2014. [ DOI ]
[39] Wolfgang Schröder-Preikschat. Embedded Computing Systems in the Multi-Core Era. Invited talk, Victoria University of Wellington, New Zealand, February 28, 2014.
[38] Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf and Jürgen Becker. The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. In Proceedings of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, February 25, 2014.
[37] Wolfgang Schröder-Preikschat. Embedded Computing Systems in the Multi-Core Era. Invited talk, Multicore World 2014, Auckland, New Zealand, February 25, 2014.
[36] Janmartin Jahn. Resource Allocation for Software Pipelines in Many-core Systems. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2014.
[35] Michael Bader. On the Performance of Adaptive Mesh-Based Simulations on Modern HPC Architectures. Invited presentation at SIAM Conference on Parallel Processing in Scientific Computing - SIAM PP 2014, February, 2014. [ http ]
[34] Artjom Grudnitsky, Lars Bauer and Jörg Henkel. MORP: Makespan Optimization for Processors with an Embedded Reconfigurable Fabric. In Proceedings of the 22nd ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pages 127–136, February 2014. [ DOI ]
[33] Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann and Wolfgang Schröder-Preikschat. Resource-Aware Harris Corner Detection based on Adaptive Pruning. In Proceedings of the Conference on Architecture of Computing Systems (ARCS), pages 1–12. Springer, February 2014. [ DOI ]
[32] Sascha Roloff, Frank Hannig and Jürgen Teich. Towards Actor-oriented Programming on PGAS-based Multicore Architectures. In Workshop Proceedings of the 27th International Conference on Architecture of Computing Systems (ARCS). VDE Verlag, February 2014.
[31] C. Tradowsky, T. Gädeke, T. Bruckschlögl, W. Stork, K.-D. Müller-Glaser and J. Becker. SmartLoCore: A Concept for an Adaptive Power-Aware Localization Processor. In Parallel, Distributed and Network-Based Processing (PDP), 2014 22nd Euromicro International Conference on, pages 478-481, February 2014. [ DOI ]
[30] Michael Bader, Alexander Breuer, Wolfgang Hölzl and Sebastian Rettenberger. Vectorization of an Augmented Riemann Solver for the Shallow Water Equations. In Proceedings of the 2014 International Conference on High Performance Computing and Simulation (HPCS 2014), pages 193–201. IEEE, 2014.
[29] Martin Barke. Aging Aware Robustness Validation of Digital Integrated Circuits. Dissertation, Technische Universität München, Fakultät für Elektrotechnik und Informationstechnik, 2014.
[28] Matthias Braun, Sebastian Buchwald, Manuel Mohr and Andreas Zwinkau. Dynamic X10: Resource-Aware Programming for Higher Efficiency. Technical Report 8, Karlsruhe Institute of Technology, 2014. [ http ]
[27] Daniel Danner, Rainer Müller, Wolfgang Schröder-Preikschat, Wanja Hofer and Daniel Lohmann. Safer Sloth: Efficient, Hardware-Tailored Memory Protection. In Proceedings of the 20th IEEE International Symposium on Real-Time and Embedded Technology and Applications (RTAS '14), pages 37–47. IEEE Computer Society Press, 2014. [ http ]
[26] Felix Freiling, Mykola Protsenko and Yan Zhuang. An Empirical Evaluation of Software Obfuscation Techniques applied to Android APKs. In International Workshop on Data Protection in Mobile and Pervasive Computing, 2014.
[25] Stephanie Friederich, Jan Heisswolf, David May and Jürgen Becker. Hardware prototyping and software debugging of multi-core architectures. In Proceedings of the Synopsys Users Group Conference (SNUG), 2014.
[24] Johannes Götzfried and Tilo Müller. Mutual Authentication and Trust Bootstrapping towards Secure Disk Encryption. In Transactions on Information and System Security (TISSEC), 2014. [ DOI ] [ http ]
[23] Elisabeth Glocker, Qingqing Chen, Asheque M. Zaidi, Ulf Schlichtmann and Doris Schmitt-Landsiedel. Emulierung eines ASIC-Leistungsverbrauchs- und Temperaturmonitorsystems für FPGA-Prototyping eines ressourcengewahren Computersystems. In 16. Workshop Analogschaltungen, Wien, Österreich, 2014.
[22] E. Glocker, S. Boppu, Q. Chen, U. Schlichtmann, J. Teich and D. Schmitt-Landsiedel. Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs). Advances in Radio Science, 12:103–109, 2014. [ DOI ]
[21] Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase and Oliver Reiche. Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Transactions on Embedded Computing Systems (TECS), 13(4s):133:1–133:29, 2014. [ DOI ]
[20] Jan Heisswolf, Aurang Zaib, Andreas Zwinkau, Sebastian Kobbe, Andreas Weichslgartner, Jürgen Teich, Jörg Henkel, Gregor Snelting, Andreas Herkersdorf and Jürgen Becker. CAP: Communication Aware Programming. In 51th ACM/EDAC/IEEE Design Automation Conference (DAC), pages 105:1–105:6, 2014.
[19] Wanja Hofer. Sloth: The Virtue and Vice of Latency Hiding in Hardware-Centric Operating Systems. Dissertation, Friedrich-Alexander-Universität Erlangen-Nürnberg, 2014. [ http ]
[18] Veit B. Kleeberger, Martin Barke, Christoph Werner, Doris Schmitt-Landsiedel and Ulf Schlichtmann. A Compact Model for NBTI Degradation and Recovery under Use-Profile Variations and its Application to Aging Analysis of Digital Integrated Circuits. Microelectronics Reliability, 54(6–7):1083–1089, 2014. [ DOI ]
[17] Christopher Kugler and Tilo Müller. SCADS: Separated Control- and Data-Stacks (Best Student Paper Award). In 10th International Conference on Security and Privacy in Communication Networks, 2014. [ http ]
[16] Dominik Lorenz, Martin Barke and Ulf Schlichtmann. Monitoring of aging in integrated circuits by identifying possible critical paths. Microelectronics Reliability, 54:1075 - 1082, 2014. [ DOI ]
[15] David May and Walter Stechele. Improving the significance of probabilistic circuit fault emulations. In 2014 IEEE 20th International On-Line Testing Symposium (IOLTS), pages 128–133, 2014.
[14] Rainer Müller, Daniel Danner, Wolfgang Schröder-Preikschat and Daniel Lohmann. MultiSloth: An Efficient Multi-Core RTOS using Hardware-Based Scheduling. In Proceedings of the 26th Euromicro Conference on Real-Time Systems (ECRTS '14), pages 289-198. IEEE Computer Society Press, 2014. [ DOI ]
[13] Roman Plyaskin. Fast and Accurate Performance Simulation of Out-of-order Processing Cores in Embedded Systems. Dissertation, Technische Universität München, Fakultät für Elektrotechnik und Informationstechnik, 2014.
[12] Nasim Pour Aryan, A. Listl, L. Heiss, C. Yilmaz, G. Georgakos and D. Schmitt-Landsiedel. From an analytic NBTI device model to reliability assessment of complex digital circuits. In International On-Line Testing Symposium (IOLTS), pages 19-24, 2014.
[11] Martin Schreiber. Cluster-Based Parallelization of Simulations on Dynamically Adaptive Grids and Dynamic Resource Management. Dissertation, Institut für Informatik, Technische Universität München, 2014. [ http ]
[10] Muhammad Shafique, Lars Bauer and Jörg Henkel. Adaptive Energy Management for Dynamically Reconfigurable Processors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 33(1):50–63, January 2014. [ DOI ]
[9] Muhammad Shafique and Jörg Henkel. Low Power Design of the Next-Generation High Efficiency Video Coding. In 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 274–281, January 2014. [ DOI ]
[8] Gregor Snelting, Dennis Giffhorn, Jürgen Graf, Christian Hammer, Martin Hecker, Martin Mohr and Daniel Wasserrab. Checking Probabilistic Noninterference Using JOANA. IT - Information Technology, 2014. invited article, currently under review [ http ]
[7] Tobias Weinzierl, Roland Wittmann, Kristof Unterweger, Michael Bader, Alexander Breuer and Sebastian Rettenberger. Hardware-aware block size tailoring on adaptive spacetree grids for shallow water waves. In HiStencils 2014 – 1st International Workshop on High-Performance Stencil Computations, 2014.
[6] Johny Paul, Walter Stechele, Manfred Kröhnert and Tamim Asfour. Resource-aware programming for robotic vision. arXiv preprint arXiv:1405.2908, First Workshop on Resource awareness and adaptivity in multi-core computing; co-located with IEEE European Test Symposium (ETS)2014.
[5] Martin Schreiber. Cluster-Based Parallelization of Simulations on Dynamically Adaptive Grids and Dynamic Resource Management. Dissertation, Technische Universität München, Fakultät für Informatik, 2014.
[4] D. Schiebener, A. Ude and T. Asfour. Physical Interaction for Segmentation of Unknown Textured and Non-textured Rigid Objects. In IEEE International Conference on Robotics and Automation (ICRA), 2014.
[3] Peter Kaiser, David Gonzalez-Aguirre, Fabian Schültje, J\'ulia Borr\`as, Nikolaus Vahrenkamp and Tamim Asfour. Extracting Whole-Body Affordances from Multimodal Exploration. In IEEE/RAS International Conference on Humanoid Robots (Humanoids), pages 1036–1043, 2014.
[2] M. Do, J. Schill, J. Ernesti and T. Asfour. Learn to Wipe: A Case Study of Structural Bootstrapping from Sensorimotor Experience. In IEEE International Conference on Robotics and Automation (ICRA), 2014.
[1] Santiago Pagani, Heba Khdr, Waqaas Munawar, Jian-Jia Chen, Muhammad Shafique, Minming Li and Jörg Henkel. TSP: Thermal safe power: Efficient power budgeting for many-core systems in dark silicon. In Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, pages 1–10, 2014.

2013

[84] Timo Stripf. Softwareframework für Prozessoren mit variablen Befehlssatzarchitekturen. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2013.
[83] Santiago Pagani and Jian-Jia Chen. Energy Efficient Task Partitioning based on the Single Frequency Approximation Scheme. In Proceedings of the 34th IEEE Real-Time Systems Symposium (RTSS), pages 308-318, December 2013. [ DOI ]
[82] Jürgen Teich. Invasive Computing – The Quest for Many-Core Efficiency and Predictability. Keynote Talk, Sixth Swedish Workshop on Multicore Computing, Halmstad, Sweden, November 25, 2013.
[81] Michael Bader. Exploiting locality properties of space-filling curves in scientific computing. Colloquium talk at TU Eindhoven, November, 2013.
[80] Muhammad Usman Karim Khan, Muhammad Shafique and Jörg Henkel. AMBER: Adaptive Energy Management for On-Chip Hybrid Video Memories. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 405–412, November 2013.
[79] Wolfgang Schröder-Preikschat. Embedded Computing Systems in the Multi-Core Era. Invited keynote, 3rd Brazilian Symposium on Computing Systems Engineering (SBESC 2013), Niterói, Brazil, November 5, 2013.
[78] Muhammad Shafique and Jörg Henkel. Agent-Based Distributed Power Management for Kilo-Core Processors. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 153–160, November 2013.
[77] Jürgen Teich. Invasive Computing - The Quest for Many-Core Efficiency and Predictability. Invited Talk, 5th tubs.CITY Symposium, Managing change and autonomy or critical applications, Braunschweig, Germany, October 30, 2013.
[76] Peter Figuli, Carsten Tradowsky, Nadine Gaertner and Jürgen Becker. ViSA: A Highly Efficient Slot Architecture Enabling Multi-Objective ASIP Cores. In International Symposium on System on Chip (SoC), pages 1–8, October 2013. [ DOI ]
[75] Manuel Mohr, Artjom Grudnitsky, Tobias Modschiedler, Lars Bauer, Sebastian Hack and Jörg Henkel. Hardware Acceleration for Programs in SSA Form. In International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), October 2013. [ DOI ]
[74] Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann and Wolfgang Schröder-Preikschat. A Resource-Aware Nearest Neighbor Search Algorithm for K-Dimensional Trees. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pages 80–87. IEEE Computer Society Press, October 2013.
[73] Martin Schreiber, Christoph Riesinger, Tobias Neckel and Hans-Joachim Bungartz. Invasive Compute Balancing for Applications with Hybrid Parallelization. In Proceedings of the International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). IEEE, October 2013.
[72] Martin Schreiber, Tobias Weinzierl and Hans-Joachim Bungartz. SFC-based Communication Metadata Encoding for Adaptive Mesh Refinement. In Proceedings of the International Conference on Parallel Computing (ParCo), October 2013.
[71] Éricles Sousa, Alexandru Tanase, Frank Hannig and Jürgen Teich. Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pages 88–95. IEEE, October 2013.
[70] Éricles Sousa, Alexandru Tanase, Frank Hannig and Jürgen Teich. A Prototype of an Adaptive Computer Vision Algorithm on an MPSoC Architecture. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pages 361–362. IEEE, October 2013.
[69] Tamim Asfour, Julian Schill, Heiner Peters, Cornelius Klas, Jens Bücker, Christian Sander, Stefan Schulz, Artem Kargov, Tino Werner and Volker Bartenbach. ARMAR-4: A 63 DOF Torque Controlled Humanoid Robot. In IEEE/RAS International Conference on Humanoid Robots (Humanoids), pages 390–396, October 2013.
[68] Jürgen Teich. The Invasive Computing Paradigm as a Solution for Highly Adaptive and Efficient Multi-core Systems. Talk, Special Session on Run-Time Adaption for Highly-Compley Multi-Core Systems, CODES+ISSS 2013, Montral, Canada, September 30, 2013.
[67] Wolfgang Schröder-Preikschat. Virtuelle Maschinen. Eingeladener Vortrag, INFORMATIK 2013, Workshop `Virtualisierung: gestern, heute und morgen', Koblenz, September 19, 2013.
[66] Elisabeth Glocker, Srinivas Boppu, Qingqing Chen, Ulf Schlichtmann, Jürgen Teich and Doris Schmitt-Landsiedel. Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs) on FPGA. In Kleinheubacher Tagung 2013, September 2013.
[65] Fazal Hameed, Lars Bauer and Jörg Henkel. Simultaneously Optimizing DRAM Cache Hit Latency and Miss Rate via Novel Set Mapping Policies. In International Conference on Compilers Architecture and Synthesis for Embedded Systems (CASES), September 2013. [ DOI ]
[64] Fazal Hameed, Lars Bauer and Jörg Henkel. Reducing Inter-Core Cache Contention with an Adaptive Bank Mapping Policy in DRAM Cache. In International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2013. [ DOI ]
[63] J. Heisswolf, S. Bischof, M. Rueckauer and Jürgen Becker. Efficient Memory Access in 2D Mesh NoC Architectures using High Bandwidth Routers. In Proceedings of the 26th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 1-6, September 2013. [ DOI ]
[62] Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran and Jürgen Teich. Run-Time Adaptation for Highly-Complex Multi-Core Systems. In Proceedings of the IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2013. [ DOI ]
[61] Alexandru Tanase, Vahid Lari, Frank Hannig and Jürgen Teich. Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing. In Proceedings of the International Conference on Parallel Computing (ParCo), pages 53–62, September 2013. [ DOI ]
[60] Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker and Andreas Herkersdorf. AUTO-GS: Self-optimization of NoC Traffic Through Hardware Managed Virtual Connections. In Proceedings of the 16th Euromicro Conference on Digital System Design (DSD), pages 761–768. IEEE, September 2013. [ DOI ]
[59] Gabor Drescher, Timo Hönig, Sebastian Maier, Benjamin Oechslein and Wolfgang Schröder-Preikschat. A Scalability-Aware Kernel Executive for Many-Core Operating Systems. In Proceedings of the International Workshop on Runtime and Operating Systems for the Many-core Era (ROME 2013), pages 1–10. Springer-Verlag, August 26, 2013. [ DOI ] [ http ]
[58] Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf and Jürgen Becker. Virtual networks – distributed communication resource management. ACM Trans. Reconfigurable Technol. Syst., 6(2):8:1–8:14, August 2013. [ DOI ]
[57] Santiago Pagani and Jian-Jia Chen. Energy Efficiency Analysis for the Single Frequency Approximation (SFA) Scheme. In Proceedings of the 19th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pages 82-91, August 2013. \textbfBest Paper Award [ DOI ]
[56] Martin Schreiber, Tobias Weinzierl and Hans-Joachim Bungartz. Cluster Optimization and Parallelization of Simulations with Dynamically Adaptive Grids. In Euro-Par 2013, August 2013.
[55] Carsten Tradowsky, Tanja Harbaum, Shaver Deyerle and Jürgen Becker. LImbiC: An Adaptable Architecture Description Language Model for Developing an Application-Specific Image Processor. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 34–39, August 2013. [ DOI ]
[54] Srinivas Boppu, Frank Hannig and Jürgen Teich. Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators. In Proceedings of the 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 10–17. IEEE, June 2013. [ DOI ]
[53] Janmartin Jahn, Santiago Pagani, Sebastian Kobbe, Jian-Jia Chen and Jörg Henkel. Optimizations for Configuring and Mapping Software Pipelines in ManyCore. In IEEE/ACM 50th Design Automation Conference (DAC), June 2013. [ DOI ]
[52] Vahid Lari, Srinivas Boppu, Frank Hannig, Jürgen Teich and Troy Scott. Hybrid Prototyping of Tightly-Coupled Processor Arrays for MPSoC Designs. Designer Track Poster Presentation at the 50th Design Automation Conference (DAC), Austin, TX, USA, June, 2013.
[51] Sascha Roloff, Andreas Weichslgartner, Jan Heißwolf, Frank Hannig and Jürgen Teich. NoC Simulation in Heterogeneous Architectures for PGAS Programming Model. In Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems (M-SCOPES), pages 77–85. ACM, June 2013. [ DOI ]
[50] Amit Singh, Muhammad Shafique, Akash Kumar and Jörg Henkel. Mapping on Multi/Many Core Systems: Survey of Current and Emerging Trends. In IEEE/ACM 50th Design Automation Conference (DAC), June 2013. [ DOI ]
[49] Jürgen Teich, Alexandru Tanase and Frank Hannig. Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays. In Proceedings of the 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 1–9. IEEE, June 2013. Best Paper Award [ DOI ]
[48] Srinivas Boppu, Vahid Lari, Frank Hannig and Jürgen Teich. Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures. In Proceedings of the Synopsys Users Group Conference (SNUG), May 14, 2013.
[47] Martin Barke, Veit B. Kleeberger, Christoph Werner, Doris Schmitt-Landsiedel and Ulf Schlichtmann. Analysis of Aging Mitigation Techniques for Digital Circuits Considering Recovery Effects. In edaWorkshop, May 2013.
[46] Frank Hannig, Moritz Schmid, Vahid Lari, Srinivas Boppu and Jürgen Teich. System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures. In Proceedings of the ACM International Conference on Computing Frontiers (CF), pages 2:1–2:4. ACM, May 2013. [ DOI ]
[45] Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Ralf König, T. Wild, A. Herkersdorf, Jürgen Teich and Jürgen Becker. Hardware Supported Adaptive Data Collection for Networks on Chip. In Proceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum (IPDPSW), pages 153-162, May 2013. [ DOI ]
[44] Bruno Zatt, Muhammad Shafique, Sergio Bampi and Jörg Henkel. 3D Video Coding for Embedded Devices: Energy Efficient Algorithms and Architectures. In Springer Science+Business Media, LLC, May 2013.
[43] Jürgen Teich. Invasive Computing - The Quest for Many-Core Efficiency and Predictability. Invited Keynote, Doctoral Workshop GNARP 2013 (The 20th annual ASCI Computing Workshop), Soesterberg, The Netherlands, April 25, 2013.
[42] Jürgen Teich. More Cores = Less Predictability? Invited Talk, University of Amsterdam, The Netherlands, April 24, 2013.
[41] Jürgen Teich. More Cores = Less Predictability? Innovation Forum Smart Systems, Bavarian Information and Communication Technology Cluster (BICCNet), Munich, Germany, April 18, 2013.
[40] Éricles Sousa, Alexandru Tanase, Vahid Lari, Frank Hannig, Jürgen Teich, Johny Paul, Walter Stechele, Manfred Kröhnert and Tamim Asfour. Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays. In Proceedings of the 25th Workshop on Parallel Systems and Algorithms (PARS), pages 80–89. Gesellschaft für Informatik e.V., April 2013.
[39] Janmartin Jahn and Jörg Henkel. Pipelets: Self-Organizing Software Pipelines for Many Core Architectures. In Proceedings of Design, Automation and Test in Europe Conference (DATE), March 2013. [ DOI ]
[38] Vahid Lari, Srinivas Boppu, Frank Hannig, Shravan Muddasani, Boris Kuzmin and Jürgen Teich. Resource-Aware Video Processing on Tightly-Coupled Processor Arrays. Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Grenoble, France, March, 2013. [ http ]
[37] Bing Li, Ning Chen, Yang Xu and Ulf Schlichtmann. On Timing Model Extraction and Hierachical Statistical Timing Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 32(3):367–380, March 2013.
[36] C. Pham, J. Heisswolf, S. Wenner, Z. Al-Ars, J.A. Becker and K.L.M. Bertels. Hybrid Interconnect Design for Heterogeneous Hardware Accelerators. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 843–846, March 2013. [ DOI ]
[35] Felipe Sampaio, Bruno Zatt, Muhammad Shafique, Luciano Agostini, Sergio Bampi and Jörg Henkel. Energy-Efficient Memory Hierarchy for Motion and Disparity Estimation in Multiview Video Coding. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 665-670, March 2013. [ DOI ]
[34] Muhammad Shafique, Benjamin Vogel and Jörg Henkel. Self-Adaptive Hybrid Dynamic Power Management for Many-Core Systems. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 51-56, March 2013. [ DOI ]
[33] Sefan Wildermann, Tobias Ziermann and Jürgen Teich. Game-Theoretic Analysis of Decentralized Core Allocation Schemes on Many-core Systems. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 1498–1503, March 2013. [ DOI ]
[32] Frank Hannig. Resource-Aware Computing on Domain-Specific Accelerators. In Proceedings of the 10st Workshop on Optimizations for DSP and Embedded Systems (ODES), pages 35. ACM, February 24, 2013. Keynote [ DOI ]
[31] Jürgen Teich. Invasive Computing - The Quest for Many-Core Efficiency and Predictability. Invited Keynote Speech, 26th International Conference on Architecture of Computing Systems (ARCS), Prague, Czech Republic, February 20, 2013.
[30] Lars Braun. Methoden zur Erstellung eines laufzeitadaptiven und zweidimensional rekonfigurierbaren Systems. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2013.
[29] Jürgen Teich. Safe(r) Loop Computations on Multi-Cores. Invited Talk, 2nd Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms (DITAM 2013), Berlin, Germany, January 22, 2013.
[28] David Israel Gonzalez-Aguirre. Model-Based Environmental Visual Perception for Humanoid Robots. Dissertation, Institute for Anthropomatics and Robotics; Department of Informatics, Karlsruhe Institute of Technology, Germany, 2013.
[27] Kimon Karras. A Network Processor Architecture for High Speed Carrier Grade Ethernet Networks. Dissertation, Fakultät für Elektrotechnik und Informationstechnik, Technische Universität München, Germany, 2013.
[26] Richard Membarth. Code Generation for GPU Accelerators from a Domain-Specific Language for Medical Imaging. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2013.
[25] Markus Przybylski. Greifplanung basierend auf Objektsymmetrieeigenschaften. Dissertation, Institute for Anthropomatics and Robotics; Department of Informatics, Karlsruhe Institute of Technology, Germany, 2013.
[24] Matthias Braun, Sebastian Buchwald, Sebastian Hack, Roland Leißa, Christoph Mallon and Andreas Zwinkau. Simple and Efficient Construction of Static Single Assignment Form. In Compiler Construction, pages 102–122. Springer, 2013. [ DOI ]
[23] Hans-Joachim Bungartz, Christoph Riesinger, Martin Schreiber, Gregor Snelting and Andreas Zwinkau. Invasive Computing in HPC with X10. In X10 Workshop (X10'13), pages 12–19. ACM, 2013. [ DOI ]
[22] Patrick Flick, Peter Sanders and Jochen Speck. Malleable Sorting. In Parallel Distributed Processing (IPDPS), 2013 IEEE 27th International Symposium on, pages 418–426, 2013. [ DOI ]
[21] Elisabeth Glocker and Doris Schmitt-Landsiedel. Modeling of Temperature Scenarios in a Multicore Processor System. , 11:219–225, 2013. Advances in Radio Science (ARS), Volume 11 [ DOI ]
[20] Jan Heisswolf, Ralf König, M. Kupper and Jürgen Becker. Multiple Hard Latency and Throughput Guarantees for Packet Switching Networks on Chip. Computers & Electrical Engineering, 2013. [ DOI ]
[19] Jan Heisswolf, Maximilian Singh, Martin Kupper, Ralf Koenig and Juergen Becker. Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2013.
[18] Reinhard Tartler. Mastering Variability Challenges in Linux and related Highly-Configurable System Software. Dissertation, Friedrich-Alexander-Universität Erlangen-Nürnberg, 2013.
[17] Anil Kurmus, Reinhard Tartler, Daniela Dorneanu, Bernhard Heinloth, Valentin Rothberg, Andreas Ruprecht, Rüdiger Kapitza, Wolfgang Schröder-Preikschat and Daniel Lohmann. Attack Surface Metrics and Automated Compile-Time OS Kernel Tailoring. In Proceedings of the 20th Network and Distributed System Security Symposium (NDSS 2013), pages 1–8, 2013.
[16] Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid and Jürgen Teich. Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays. ACM Transactions on Design Automation of Electronic Systems (TODAES), 18(1):2:1–2:25, January 2013. [ DOI ]
[15] Yury Oleynik, Michael Gerndt and Andres Avila. A Data Model for Performance Dynamics Exploration. In 15th IEEE International Conference on High Performance Computing and Communications (HPCC-13), 2013.
[14] Luciano Ost, Rafael Garibotti, Gilles Sassatelli, Gabriel Marchesan Almeida, Remi Busseuil, Anastasiia Butko, Michel Robert and Jurgen Becker. Novel Techniques for Smart Adaptive Multiprocessor SoCs. IEEE Transactions on Computers, 99:1, 2013. PrePrints [ DOI ]
[13] Peter Sanders, Jochen Speck and Raoul Steffen. Work-efficient matrix inversion in polylogarithmic time. In Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures, pages 214–221. ACM, 2013. [ DOI ]
[12] Jürgen Teich, Wolfgang Schröder-Preikschat and Andreas Herkersdorf. Invasive Computing - Common Terms and Granularity of Invasion. CoRR, abs/1304.60672013.
[11] Josef Weidendorfer. Data Transfer Requirement Analysis with Bandwidth Curves. In Europar 2013 Workshop proceedings. 6th Workshop on Productivity and Performance, 2013.
[10] K. Welke, D. Schiebener, T. Asfour and R. Dillmann. Gaze selection during manipulation. In IEEE International Conference on Robotics and Automation (ICRA), 2013.
[9] Kai Welke, Nikolaus Vahrenkamp, Mirko Wächter, Manfred Kröhnert and Tamim Asfour. The ArmarX Framework - Supporting high level robot programming through state disclosure. In Informatik 2013 Workshop on robot control architectures, 2013.
[8] Martin Wirnshofer. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Series in Advanced Microelectronics, 2013.
[7] Tobias Ziermann. Self-organization and Optimization of Priority-based Communication Buses. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2013.
[6] Tobias Ziermann, Stefan Wildermann and Jürgen Teich. Self-organizing Core Allocation. In Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS). ACM German Chapter, Gesellschaft für Informatik e.V., 2013.
[5] Andreas Zwinkau, Sebastian Buchwald and Gregor Snelting. InvadeX10 Documentation v0.5. Technical Report 7, Karlsruhe Institute of Technology, 2013. [ http ]
[4] Martin Wirnshofer. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Dissertation, Technical University of Munich, 2013.
[3] Marion Weinzierl. Hybrid Geometric-Algebraic Matrix-Free Multigrid on Spacetrees. Dissertation, Technische Universität München, Fakultät für Informatik, 2013.
[2] Job Noorman, Pieter Agten, Wilfried Daniels, Raoul Strackx, Anthony Van Herrewege, Christophe Huygens, Bart Preneel, Ingrid Verbauwhede and Frank Piessens. Sancus: Low-cost Trustworthy Extensible Networked Devices with a Zero-software Trusted Computing Base. In Proceedings of the 22nd USENIX Conference on Security, 2013.
[1] D. Schiebener, J. Morimoto, T. Asfour and A. Ude. Integrating visual perception and manipulation for autonomous learning of object representations. Adaptive Behavior, 21(5):328-345, 2013.

2012

[75] Wanja Hofer, Daniel Danner, Rainer Müller, Fabian Scheler, Wolfgang Schröder-Preikschat and Daniel Lohmann. Sloth on Time: Efficient Hardware-Based Scheduling for Time-Triggered RTOS. In Proceedings of the 33rd IEEE International Symposium on Real-Time Systems (RTSS '12), pages 237–247. IEEE Computer Society Press, December 2012. [ DOI ]
[74] Carsten Tradowsky, Enrique Cordero, Thorsten Deuser, Michael Hübner and Jürgen Becker. Determination of On-Chip Temperature Gradients on Reconfigurable Hardware. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), pages 1–8, December 2012. [ DOI ]
[73] Martin Wirnshofer, Nasim Pour Aryan, Leonhard Heiss, Doris Schmitt-Landsiedel and Georg Georgakos. On-Line Supply Voltage Scaling based on In Situ Delay Monitoring to Adapt for PVTA Variations. Journal of Circuits, Systems and Computers, 21(08):December 2012. [ DOI ]
[72] Frank Hannig. Invasive Tightly-Coupled Processor Arrays. Talk, 1st International Workshop on Domain-Specific Multicore Computing (DSMC) at International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, November 8, 2012.
[71] Frank Hannig. Why do we see more and more domain-specific accelerators in multi-processor systems? Guest Lecture at University of California, Riverside in CS 287 Colloquium in Computer Science, Riverside, CA, USA, November 9, 2012.
[70] Bing Li, Ning Chen and Ulf Schlichtmann. Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 1670–1683, November 2012.
[69] David Schiebener, Julian Schill and Tamim Asfour. Discovery, Segmentation and Reactive Grasping of Unknown Objects. In 12th IEEE-RAS International Conference on Humanoid Robots (Humanoids), pages 71–77, November 2012.
[68] Jürgen Teich. Invasive Computing - or - How to Tame 1000+ Cores on a Chip? Invited Talk, IBM, Böblingen, Germany, October 26, 2012.
[67] Jürgen Teich. Invasive Computing - or - How to Tame 1000+ Cores on a Chip. Models and Assistive Tools for Programming Emerging Architectures, Invited Talk, HiPEAC CSW 2012, Ghent, Belgium, October 15, 2012.
[66] Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari and Jürgen Teich. A Prototype of an Invasive Tightly-Coupled Processor Array. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pages 393–394. IEEE, October 2012.
[65] Wolfgang Schröder-Preikschat. Invasive Computing: A Systems-Programming Perspective. Invited talk, Université Pierre et Marie Curie (UPMC), Laboratoire d'Informatique de Paris (LIP6), Paris, September 28, 2012.
[64] Jürgen Teich. Invasive Computing - or - How to Tame 1000+ Cores on a Chip? Invited Talk, Intel, Braunschweig, Germany, September 20, 2012.
[63] N. Chen, B. Li and U. Schlichtmann. Iterative timing analysis based on nonlinear and interdependent flipflop modelling. Circuits, Devices Systems, IET, 6(5):330–337, September 2012. [ DOI ]
[62] Michael Gerndt, Frank Hannig, Andreas Herkersdorf, Andreas Hollmann, Marcel Meyer, Sascha Roloff, Josef Weidendorfer, Thomas Wild and Aurang Zaib. An Integrated Simulation Framework for Invasive Computing. In Proceedings of the Forum on Specification and Design Languages (FDL), pages 209–216. IEEE, September 2012.
[61] Michael Gerndt, Andreas Hollmann, Marcel Meyer, Martin Schreiber and Josef Weidendorfer. Invasive computing with iOMP. In Proceedings of the Forum on Specification and Design Languages (FDL), pages 225–231, September 2012.
[60] Jürgen Teich, Andreas Weichslgartner, Benjamin Oechslein and Wolfgang Schröder-Preikschat. Invasive Computing – Concepts and Overheads. In Proceedings of the Forum on Specification and Design Languages (FDL), pages 193–200, September 2012.
[59] Dominik Lorenz, Martin Barke and Ulf Schlichtmann. Efficiently analyzing the impact of aging effects on large integrated circuits. In Microelectronics Reliability, pages 1546–1552, August 2012. [ DOI ]
[58] Jürgen Teich. Invasive Computing - or - How to Tame 1000+ Cores on a Chip? Invited Talk, University of Auckland, New Zealand, August 9, 2012.
[57] Janmartin Jahn, Sebastian Kobbe, Santiago Pagani, Jian-Jia Chen and Jörg Henkel. Work in Progress: Malleable Software Pipelines for Efficient Many-core System Utilization. In Proceedings of the 6th Many-core Applications Research Community (MARC) Symposium, pages 30–33. ONERA, The French Aerospace Lab, July 19, 2012. [ http ]
[56] Christian Schuck. Design and Synthesis of Organic Computing Hardware Architectures. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2012.
[55] Michael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg Henkel and Jürgen Becker. Adaptive Processor Architecture. In International Conference on Embedded Computer Systems (SAMOS), pages 244–251, July 2012. Invited paper [ DOI ]
[54] Jan Heisswolf, Ralf König and Jürgen Becker. A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling. In Parallel and Distributed Processing with Applications (ISPA), 2012 IEEE 10th International Symposium on, pages 625–632, July 2012. [ DOI ]
[53] Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig and Jürgen Teich. Design of Low Power On-Chip Processor Arrays. In Proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pages 165–168. IEEE Computer Society, July 2012. [ DOI ]
[52] Sascha Roloff, Frank Hannig and Jürgen Teich. Simulation of Resource-Aware Applications on Heterogeneous Architectures. In Proceedings of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), pages 127–130, July 2012.
[51] Alexandru Tanase, Frank Hannig and Jürgen Teich. Symbolic Loop Parallelization of Static Control Programs. In Proceedings of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), pages 33–36, July 2012.
[50] Jürgen Teich. Domain-specific and resource-aware computing on multi-core architectures. HiPEAC Summer School ACACES, Lecture, Lecture, Fiuggi, Italy, July 8, 2012.
[49] Stefan Wildermann. Systematic Design of Self-Adaptive Embedded Systems with Applications in Image Processing. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2012.
[48] Timo Hönig, Rüdiger Kapitza and Wolfgang Schröder-Preikschat. ProSEEP: A Proactive Approach to Energy-Aware Programming. June 2012. Poster.
[47] Matthias Kühnle. IP-based Reconfigurable System-on-Chip Design and Synthesis. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2012.
[46] Alexandru Tanase, Frank Hannig and Jürgen Teich. Towards Symbolic Loop Parallelization for Tightly-Coupled Processor Arrays. Work-In-Progress Presentation at the 49th Design Automation Conference (DAC), San Francisco, USA, June, 2012.
[45] Carsten Tradowsky, Florian Thoma, Michael Hübner and Jürgen Becker. LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture. In 7th IEEE International Symposium on Industrial Embedded Systems (SIES'12), pages 279–282, June 2012. Best Work-in-Progress (WiP) Paper Award [ DOI ]
[44] Jörg Henkel. i-Core: Adaptive Computing for Multi-core Architectures. Embedded System Design from MultiMedia to Cloud, Hong Kong, Invited Talk, May 18, 2012.
[43] Lars Bauer, Artjom Grudnitsky, Muhammad Shafique and Jörg Henkel. PATS: a Performance Aware Task Scheduler for Runtime Reconfigurable Processors. In 20th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 208–215, May 2012. [ DOI ]
[42] Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf and Jürgen Becker. Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. In Proceedings of the 2012 IEEE 26th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum (IPDPSW), pages 234–241, May 2012. [ DOI ]
[41] Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner and Wieland Eckert. Generating Device-specific GPU Code for Local Operators in Medical Imaging. In Proceedings of the 26th IEEE International Parallel & Distributed Processing Symposium (IPDPS), pages 569–581, May 2012. [ DOI ]
[40] Sascha Roloff, Frank Hannig and Jürgen Teich. Fast Architecture Evaluation of Heterogeneous MPSoCs by Host-Compiled Simulation. In Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 52–61. ACM Press, May 2012. [ DOI ]
[39] Jürgen Teich. Hardware/Software Co-Design: The Past, Present, and Predicting the Future. Proceedings of the IEEE, 100(Centennial-Issue):1411–1430, May 2012. [ DOI ]
[38] Carsten Tradowsky, Florian Thoma, Michael Hübner and Jürgen Becker. On Dynamic Run-Time Processor Pipeline Reconfiguration. In IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), pages 419–424, May 2012. [ DOI ]
[37] Sani R. Nassif, Veit B. Kleeberger and Ulf Schlichtmann. Goldilocks failures: not too soft, not too hard. In IEEE International Reliability Physics Symposium (IRPS), April 2012.
[36] Martin Wirnshofer, Leonhard Heiss, A.N.Kakade, Nasim Pour Aryan, Georg Georgakos and Doris Schmitt-Landsiedel. Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit. In IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pages 205–208, April 2012. [ DOI ]
[35] Jürgen Teich. Actor-Based Virtual Prototype Generation. Workshop: Quo Vadis, Virtual Platforms? Challenges and Solutions for Today and Tomorrow, Invited Talk, date 2012, Dresden, Germany, March 16, 2012.
[34] Artjom Grudnitsky, Lars Bauer and Jörg Henkel. Partial online-synthesis for mixed-grained reconfigurable architectures. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 1555–1560, March 2012. [ DOI ]
[33] Christoph Knoth, Hela Jedda and Ulf Schlichtmann. Current Source Modeling for Power and Timing Analysis at Different Supply Voltages. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 923–928, March 2012. [ DOI ]
[32] Jürgen Teich. Introduction to Invasive Computing and Overhead Analysis for a Shared-Memory MPSoC. 3rd Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures, Munich, Germany, February 29, 2012.
[31] Reinhard Tartler, Julio Sincero, Christian Dietrich, Wolfgang Schröder-Preikschat and Daniel Lohmann. Revealing and Repairing Configuration Inconsistencies in Large-Scale System Software. International Journal on Software Tools for Technology Transfer (STTT), 14(5):531–551, February 2012. [ DOI ]
[30] Isañas A. Comprés Ureña, Michael Riepen, Michael Konow and Michael Gerndt. Invasive MPI on Intel's Single-Chip Cloud Computer. In Proceedings of the 25th International Conference on Architecture of Computing System (ARCS), pages 74–85. Springer, February 2012. [ DOI ]
[29] Josef Angermeier. Concepts and Algorithms to Increase the Efficiency and Reliability of Reconfigurable Computers. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2012.
[28] Ralf König. Sierpinski Curves for Parallel Adaptive Mesh Refinement in Finite Element and Finite Volume Methods. Dissertation, Institut für Technik der Informationsverarbeitung, Karlsruhe Institute of Technology, Germany, 2012.
[27] Andreas Lochbihler. A Machine-Checked, Type-Safe Model of Java Concurrency: Language, Virtual Machine, Memory Model, and Compiler. Dissertation, Fakultät für Informatik, Karlsruher Institut für Technologie, Germany, 2012.
[26] T. Asfour. Towards High-Performance 24/7 Cognitive Humanoids. In Berlin Summit on Robotics, pages 53–61, January 5 2012.
[25] C. Böge, N. Vahrenkamp, T. Asfour and R. Dillmann. Visual Servoing for Single and Dual Arm Manipulation Tasks in Humanoid Robots. at - Automatisierungstechnik, 60(5):309–317, 2012.
[24] Michael Bader, Hans-Joachim Bungartz and Martin Schreiber. Invasive Computing on High Performance Shared Memory Systems. In Facing the Multicore-Challenge III, pages 1–12, 2012.
[23] Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf Koenig and David May. Hardware Prototyping of Novel Invasive Multicore Architectures. In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 201–206, January 2012. [ DOI ]
[22] Matthias Braun, Sebastian Buchwald, Manuel Mohr and Andreas Zwinkau. An X10 Compiler for Invasive Architectures. Technical Report 9, Karlsruhe Institute of Technology, 2012. [ http ]
[21] Peter Figuli, Michael Hübner, Romuald Girardey, F. Bapp, Thomas Bruckschlögl, Florian Thoma, Jörg Henkel and Jürgen Becker. A heterogeneous SoC Architecture with embedded virtual FPGA Cores and runtime Core Fusion. In NASA/ESA 6th Conference on Adaptive Hardware and Systems (AHS), pages 96–103, 2012. [ DOI ]
[20] Dennis Giffhorn. Slicing of Concurrent Programs and its Application to Information Flow Control. Dissertation, Karlsruher Institut für Technologie, Fakultät für Informatik, 2012.
[19] Jens Gladigau. Combining Formal Model-Based System-Level Design with SystemC Transaction Level Modeling. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2012.
[18] Elisabeth Glocker and Doris Schmitt-Landsiedel. Modeling of Temperature Scenarios in a Multicore Processor System. In Kleinheubacher Tagung 2012, 2012.
[17] Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari and Sebastian Kobbe. Invasive Manycore Architectures. In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 193–200, January 2012. [ DOI ]
[16] Julio Sincero. Variability Bugs in System Software. Dissertation, Friedrich-Alexander-Universität Erlangen-Nürnberg, 2012.
[15] Andreas Hollmann and Michael Gerndt. Invasive Computing: An Application Assisted Resource Management Approach. In Multicore Software Engineering, Performance, and Tools, 2012, Springer Berlin Heidelberg, pages 82–85. [ DOI ]
[14] Daniel Lohmann, Olaf Spinczyk, Wanja Hofer and Wolfgang Schröder-Preikschat. The Aspect-Aware Design and Implementation of the CiAO Operating-System Family. In Transactions on AOSD IX, pages 168–215. Springer-Verlag, 2012. [ DOI ]
[13] Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour and Rüdiger Dillmann. Invasive Computing for Robotic Vision. In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 207–212, January 2012. [ DOI ]
[12] Johny Paul, Andreas Laika, Christopher Claus, Walter Stechele, Adam El Sayed Auf and Erik Maehle. Real-time motion detection based on SW/HW-codesign for walking rescue robots. Journal of Real-Time Image Processing, :1–16, 2012. [ DOI ]
[11] Nasim Pour Aryan, Leonhard Heiss, Doris Schmitt-Landsiedel, Georg Georgakos and Martin Wirnshofer. Comparison of in-situ delay monitors for use in Adaptive Voltage Scaling. Advances in Radio Science (ARS), 10:215–220, 2012.
[10] Sascha Roloff, Frank Hannig and Jürgen Teich. Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs. In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 187–192, January 2012. [ DOI ]
[9] Peter Sanders and Jochen Speck. Energy Efficient Frequency Scaling and Scheduling for Malleable Tasks. In Euro-Par 2012 Parallel Processing, 2012, Springer Berlin Heidelberg, pages 167–178. [ DOI ]
[8] Martin Schreiber, Hans-Joachim Bungartz and Michael Bader. Shared Memory Parallelization of Fully-Adaptive Simulations Using a Dynamic Tree-Split and -Join Approach. In Proceedings of HiPC 2012, pages 1–10. IEEE, 2012.
[7] Reinhard Tartler, Anil Kurmus, Andreas Ruprecht, Bernhard Heinloth, Valentin Rothberg, Daniela Dorneanu, Rüdiger Kapitza, Wolfgang Schröder-Preikschat and Daniel Lohmann. Automatic OS Kernel TCB Reduction by Leveraging Compile-Time Configurability. In Proceedings of the 8th Workshop on Hot Topics in System Dependability (HotDep '12), pages 3-3. USENIX Association, 2012.
[6] N. Vahrenkamp, T. Asfour and R. Dillmann. Simultaneous Grasp and Motion Planning. IEEE Robotics and Automation Magazine, 19(2):43–57, 2012.
[5] Shailesh More. Aging Degradation and Countermeasures in Deep-submicrometer Analog and Mixed Signal Integrated Circuits. Dissertation, Technical University of Munich, 2012.
[4] Christoph Knoth. Accurate Waveform-based Timing Analysis with Systematic Current Source Models. Dissertation, Technical University of Munich, 2012.
[3] Dominik Lorenz. Aging Analysis of Digital Integrated Circuits. Dissertation, Technical University of Munich, 2012.
[2] Martin Roderus. Parallelization Strategies for Density Functional Software. Dissertation, Technische Universität München, Fakultät für Informatik, 2012.
[1] Vigh Csaba. Parallel Simulations of the Shallow Water Equations on Structured Dynamically Adaptive Triangular Grids. Dissertation, Technische Universität München, Fakultät für Informatik, 2012.

2011

[48] Alexander Klimm. Computing Architectures for Security Applications on Reconfigurable Hardware in Embedded Systems. Dissertation, Institut für Technik der Informationsverarbeitung (ITIV), Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT), 2011.
[47] Wanja Hofer, Daniel Lohmann and Wolfgang Schröder-Preikschat. Sleepy Sloth: Threads as Interrupts as Threads. In Proceedings of the 32nd IEEE International Symposium on Real-Time Systems (RTSS), pages 67–77. IEEE Computer Society, December 2011. [ DOI ]
[46] Dominik Lorenz, Martin Barke and Ulf Schlichtmann. Finding Possible Critical Paths for On-line Monitoring Of Aging in Integrated Circuits. Technical Report, Technische Universität München, 2011.
[45] Ravi Kumar Pujari, Thomas Wild, Andreas Herkersdorf, Benjamin Vogel and Jörg Henkel. Hardware Assisted Thread Assignment for RISC based MPSoCs in Invasive Computing. In Proceedings of the 13th International Symposium on Integrated Circuits (ISIC), pages 106-109, December 2011. [ DOI ]
[44] Martin Wirnshofer, Leonhard Heiss, Georg Georgakos and Doris Schmitt-Landsiedel. An Energy-Efficient Supply Voltage Scheme using In-Situ Pre-Error Detection for on-the-fly Adaptation to PVT Variations. In International Symposium on Integrated Circuits (ISIC), pages 94–97, December 2011. [ DOI ]
[43] Vahid Lari, Srinivas Boppu, Shravan Muddasani, Frank Hannig and Jürgen Teich. Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays. Talk, International Workshop on Adaptive Power Management with Machine Intelligence at International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, November 10, 2011.
[42] Srinivas Boppu, Frank Hannig, Jürgen Teich and Roberto Perez-Andrade. Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), pages 392–397. IEEE, November 2011. [ DOI ]
[41] M. Hübner, C. Tradowsky, D. Göhringer, L. Braun, F. Thoma, J. Henkel and J. Becker. Dynamic Processor Reconfiguration. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), pages 123–128, November 2011. [ DOI ]
[40] Sebastian Kobbe, Lars Bauer, Daniel Lohman, Wolfgang Schröder-Preikschat and Jörg Henkel. DistRM: Distributed Resource Management for On-Chip Many-Core Systems. In Proceedings of the IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 119–128, October 2011. [ DOI ]
[39] Ning Chen, Bing Li and Ulf Schlichtmann. Timing Modeling of Flipflops Considering Aging Effects. In International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 63–72, September 2011.
[38] Christoph Knoth, Carsten Uphoff, Sebastian Kiesel and Ulf Schlichtmann. SWAT: Simulator for Waveform-Accurate Timing including Parameter Variations and Transistor Aging. In International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 193–203, September 2011.
[37] Vahid Lari, Andriy Narovlyanskyy, Frank Hannig and Jürgen Teich. Decentralized Dynamic Resource Management Support for Massively Parallel Processor Arrays. In Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 87–94. IEEE Computer Society, September 2011. [ DOI ]
[36] Jürgen Teich. Programming Invasively Parallel – An Introduction. Pervasive Parallelism Laboratory (PPL) Seminar Talk, Stanford University, CA, USA, July 25, 2011.
[35] Jürgen Teich. Invasive Parallel Computing – An Introduction. Par Lab and AMP Lab Seminar Talk, UC Berkeley, CA, USA, July 22, 2011.
[34] Jörg Henkel, Lars Bauer, Michael Hübner and Artjom Grudnitsky. i-Core: A run-time adaptive processor for embedded multi-core systems. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), July 2011. Invited paper
[33] Veit B. Kleeberger and Ulf Schlichtmann. Reliability Analysis of Digital Circuits Considering Intrinsic Noise. In Asia Symposium on Quality Electronic Design (ASQED), July 2011.
[32] Georgia Kouveli, Frank Hannig, Jan-Hugo Lupp and Jürgen Teich. Towards Resource-Aware Programming on Intel's Single-Chip Cloud Computer Processor. In 3rd Many-core Applications Research Community (MARC) Symposium, pages 111–114. KIT Scientific Publishing, July 2011.
[31] Wolfgang Schröder-Preikschat. System Software in the Many-Core Era. Invited talk, Future Trends in SOC, Hasso-Plattner-Institut (HPI), Universität Potsdam, June 16, 2011.
[30] Lars Bauer, Muhammad Shafique and Jörg Henkel. Concepts, Architectures, and Run-time Systems for Efficient and Adaptive Reconfigurable Processors. In NASA/ESA 6th Conference on Adaptive Hardware and Systems (AHS), pages 80–87, June 2011. Invited paper; Received the MaXentric Technologies AHS Best Paper Award [ DOI ]
[29] Frank Hannig, Sascha Roloff, Gregor Snelting, Jürgen Teich and Andreas Zwinkau. Resource-Aware Programming and Simulation of MPSoC Architectures through Extension of X10. In Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 48–55. ACM Press, June 2011. [ DOI ]
[28] Johannes Zeppenfeld and Andreas Herkersdorf. Applying autonomic principles for workload management in multi-core systems on chip. In Proceedings of the 8th ACM International Conference on Autonomic Computing (ICAC), pages 3–10, June 2011. [ DOI ]
[27] Josef Angermeier, Eugen Sibirko, Rolf Wanka and Jürgen Teich. Bitonic Sorting on Dynamically Reconfigurable Architectures. In Proceedings of the International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pages 309–312, May 2011.
[26] Michael Hübner, Peter Figuli, Romuald Girardey, Dimitrios Soudris, Kostas Siozios and Jürgen Becker. A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture. In Proceedings of the International Parallel and Distributed Processing Symposium Workshops (IPDPSW), May 2011.
[25] Vahid Lari, Frank Hannig and Jürgen Teich. Distributed Resource Reservation in Massively Parallel Processor Arrays. In Proceedings of the International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pages 318–321. IEEE Computer Society, May 2011. [ DOI ]
[24] Andreas Weichslgartner, Stefan Wildermann and Jürgen Teich. Dynamic Decentralized Mapping of Tree-Structured Applications on NoC Architectures. In Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pages 201–208, May 2011. [ DOI ]
[23] Benjamin Oechslein, Jens Schedel, Jürgen Kleinöder, Lars Bauer, Jörg Henkel, Daniel Lohmann and Wolfgang Schröder-Preikschat. OctoPOS: A Parallel Operating System for Invasive Computing. In Proceedings of the International Workshop on Systems for Future Multi-Core Architectures (SFMA), pages 9–14, April 2011.
[22] Reinhard Tartler, Daniel Lohmann, Julio Cezar Rodrigues Sincero and Wolfgang Schröder-Preikschat. Feature Consistency in Compile-Time Configurable System Software. In Proceedings of the Sixth International ACM/EuroSys European Conference on Computer Systems (EuroSys), pages 47–60. ACM Press, April 2011. [ DOI ]
[21] J. Jahn, M.A. Al Faruque and Jörg Henkel. CARAT: Context-Aware Runtime Adaptive Task Migration for Multi Core Architectures. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 515–520, March 2011.
[20] Michael Bader, Hans-Joachim Bungartz, Michael Gerndt, Andreas Hollmann and Josef Weidendorfer. Invasive Programming as a Concept for HPC. In Proceedings of the 10th IASTED International Conference on Parallel and Distributed Computing and Networks 2011 (PDCN), February 2011. [ DOI ]
[19] Muhammad Shafique. Architectures for Adaptive Low-Power Embedded Multimedia Systems. Dissertation, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany, 2011.
[18] Michael Meitinger. Lastbalancierung und Resequenzierung in Netzwerkprozessoren. Dissertation, Fakultät für Elektrotechnik und Informationstechnik, Technische Universität München, Germany, 2011.
[17] Kai Welke. Memory-Based Active Visual Search for Humanoid Robots. Dissertation, Institute for Anthropomatics and Robotics; Department of Informatics, Karlsruhe Institute of Technology, Germany, 2011.
[16] T. Asfour, M. Do, K. Welke, A. Bierbaum, P. Azad, N. Vahrenkamp, S. Gärtner, A. Ude and R. Dillmann. From sensorimotor primitives to manipulation and imitation strategies in humanoid robots. Springer Tracts in Advanced Robotics, 70(STAR):363–378, 2011.
[15] P. Azad, D. Münch, T. Asfour and R. Dillmann. 6-DoF Model-based Tracking of Arbitrarily Shaped 3D Objects. In IEEE International Conference on Robotics and Automation (ICRA), pages 5204–5209, 2011.
[14] Matthias Braun, Sebastian Buchwald and Andreas Zwinkau. Firm–-A Graph-Based Intermediate Representation. Technical Report 35, Karlsruhe Institute of Technology, 2011. [ http ]
[13] Sebastian Buchwald, Andreas Zwinkau and Thomas Bersch. SSA-Based Register Allocation with PBQP. In Proceedings of the International Conference on Compiler Construction (CC), pages 42–61. Springer, 2011. [ DOI ]
[12] Hans-Joachim Bungartz, Bernhard Gatzhammer, Michael Lieb, Miriam Mehl and Tobias Neckel. Towards Multi-Phase Flow Simulations in the PDE Framework Peano. Computational Mechanics, 48(3):365–376, 2011. [ http ]
[11] Hritam Dutta. Synthesis and Exploration of Loop Accelerators for Systems-on-a-Chip. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2011.
[10] Michael Glaß. Dependability-Aware System-Level Design for Embedded Systems. Dissertation, University of Erlangen-Nuremberg, Germany, 2011.
[9] D. Hillerkuss, R. Schmogrow, T. Schellinger, M. Jordan, M. Winter, G. Huber, T. Vallaitis, R. Bonk, F. Kleinow, F. Frey, M. Roeger, S. Koenig, A. Ludwig, A. Marculescu, J. Li, M. Hoh, M. Dreschmann, J. Meyer, S. Ben Ezra, N. Narkiss, B. Nebendahl, F. Parmigiani, P. Petropoulos, B. Resan, A. Oehler, K. Weingarten, T. Ellermeyer, J. Lutz, M. Moeller, M. Huebner, J. Becker, C. Koos, W. Freude and J. Leuthold. 26 Tbit $s^-1$ line-rate super-channel transmission utilizing all-optical fast Fourier transform processing. nature photonics, (5):8, 2011. [ DOI ]
[8] Dmitrij Kissler. Power-Efficient Tightly-Coupled Processor Arrays for Digital Signal Processing. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, 2011.
[7] Dmitrij Kissler, Daniel Gran, Zoran A. Salcic, Frank Hannig and Jürgen Teich. Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays. IEEE Embedded Systems Letters, 3(2):58–61, 2011. [ DOI ]
[6] Nasim Pour Aryan, Leonhard Heiss, Doris Schmitt-Landsiedel, Georg Georgakos and Martin Wirnshofer. Comparison of In-situ Delay Monitors for Use in Adaptive Voltage Scaling. In Kleinheubacher Tagung 2011, 2011.
[5] Peter Sanders and Jochen Speck. Efficient Parallel Scheduling of Malleable Tasks. In International Parallel and Distributed Processing Symposium (IPDPS), pages 1156–1166. IEEE Computer Society, 2011. [ DOI ]
[4] Jürgen Teich, Jörg Henkel, Andreas Herkersdorf, Doris Schmitt-Landsiedel, Wolfgang Schröder-Preikschat and Gregor Snelting. Invasive Computing: An Overview. In Multiprocessor System-on-Chip – Hardware Design and Tool Integration, 2011, Springer, Berlin, Heidelberg, pages 241–268. [ DOI ]
[3] N. Vahrenkamp, P. Kaiser, T. Asfour and R. Dillmann. RDT+: A Parameter–free Algorithm for Exact Motion Planning. In IEEE International Conference on Robotics and Automation (ICRA), pages 715–722, 2011.
[2] Martin Wirnshofer, Leonard Heiss, Georg Georgakos and Doris Schmitt-Landsiedel. A Variation-Aware Adaptive Voltage Scaling Technique Based on In-Situ Delay Monitoring. In IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, pages 261–266, 2011.
[1] Norbert Krüger, Christopher Geib, Justus Piater, Ronald Petrick, Mark Steedman, Florentin Wörgötter, Aleš Ude, Tamim Asfour, Dirk Kraft, Damir Omrŏen, Alejandro Agostini and Rüdiger f Dillmann. Object–Action Complexes: Grounded abstractions of sensory–motor processes. Robotics and Autonomous Systems, 59(10):740–757, 2011.

2010

[11] Frank Hannig. Retargetable Mapping of Loop Programs on Coarse-grained Reconfigurable Arrays. Talk, International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), Scottsdale, AZ, USA, October 26, 2010.
[10] Wolfgang Schröder-Preikschat. Systemsoftware im Zeitalter mehrkerniger Prozessoren. Vortrag October 15 2010. GI-Fachgruppe Betriebssysteme, IBM, Böblingen.
[9] A. Ude, A. Gams, T. Asfour and J. Morimoto. Task-Specific Generalization of Discrete and Periodic Dynamic Movement Primitives. IEEE Transactions on Robotics, 26(5):800–815, October 2010. [ DOI ]
[8] Tom Vander Aa, Praveen Raghavan, Scott Mahlke, Bjorn De Sutter, Aviral Shrivastava and Frank Hannig. Compilation Techniques for CGRAs: Exploring All Parallelization Approaches. In Proceedings of the International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), pages 185–186. ACM, October 2010. [ DOI ]
[7] Jürgen Teich. Invasive Computing – Basic Concepts and Foreseen Benefits. Artist Network of Excellence on Embedded System Design Summer School Europe 2010, Autrans, France, Invited Tutorial, September 7, 2010.
[6] Jürgen Teich. Invasive Computing – An Overview. The University of Sydney, Australia, Invited Talk, August 9, 2010.
[5] Jürgen Teich. Invasive Computing – A Novel Parallel Computing Paradigm. Workshop Multiprocessor System-On-Chip (MPSOC): Programmability, Run-Time Support and Hardware Platforms for High Performance Applications, 47th Design Automation Conference (DAC), Anaheim, USA, Invited Talk, June 13, 2010.
[4] Wolfgang Schröder-Preikschat. Systemsoftware im Zeitalter mehrkerniger Prozessoren. Vortrag April 23 2010. Innovation Forum Embedded Systems, BICC-NET, München.
[3] Wolfgang Schröder-Preikschat. Laufzeitsysteme mehrkerniger Prozessoren - Aspekte der Synchronisation in Betriebssystemen. Eingeladener Vortrag April 13 2010. Workshop zu Multicore Architecture and Programming Model Co-Optimization (MAPCO), TU München, Kloster Seeon.
[2] G. Frantz, J. Henkel, J. Rabaey, T. Schneider, M. Wolf and U. Batur. Ultra-Low Power Signal Processing. IEEE Signal Processing Magazine, 27(2):149–154, 2010. [ DOI ]
[1] Ralf Koenig, Lars Bauer, Timo Stripf, Muhammad Shafique, Waheed Ahmed, Juergen Becker and Jörg Henkel. KAHRISMA: a novel hypermorphic reconfigurable-instruction-set multi-grained-array architecture. In Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 819–824. European Design and Automation Association, 2010.

2009

[13] Wolfgang Schröder-Preikschat. Systemsoftware im Zeitalter mehrkerniger Prozessoren. December 11 2009. Embedded Multi-Core Systems, Robert Bosch GmbH, Schwieberdingen.
[12] Amouri Abdulazim, Farhadur Arifin, Frank Hannig and Jürgen Teich. FPGA Implementation of an Invasive Computing Architecture. In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT), pages 135–142. IEEE, December 2009. [ DOI ]
[11] Christian Hammer and Gregor Snelting. Flow-Sensitive, Context-Sensitive, and Object-sensitive Information Flow Control Based on Program Dependence Graphs. International Journal of Information Security, 8(6):399–422, December 2009. [ DOI ]
[10] Wolfgang Schröder-Preikschat. Invasive Computing - Paralleles Betriebssystem einer SFB/TRR-Projektinitiative. Vortrag November 12 2009. GI-Fachgruppe Betriebssysteme, TU Dortmund, Universitätskolleg Bommerholz.
[9] Wolfgang Schröder-Preikschat. Systemsoftware im Zeitalter mehrkerniger Prozessoren. Eingeladener Vortrag November 3 2009. Vom Single-Core zum Multi-Core-Processing: Chancen und Herausforderungen für Eingebettete Systeme, Fraunhofer FIRST, Berlin.
[8] Farhadur Arifin, Richard Membarth, Amouri Abdulazim, Frank Hannig and Jürgen Teich. FSM-Controlled Architectures for Linear Invasion. In Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pages 59–64, October 2009. [ DOI ]
[7] Matthias Braun and Sebastian Hack. Register Spilling and Live-Range Splitting for SSA-Form Programs. In Proceedings of the International Conference on Compiler Construction (CC), pages 174–189. Springer, March 2009. [ DOI ]
[6] Wolfgang Schröder-Preikschat, Jörg Henkel, Lars Bauer and Daniel Lohmann. C1: Invasive Run-Time Support System ($i$RTSS). In , pages 471–528. In Teich et. al. ("Invasive Computing. "), pages 471–528.
[5] P. Azad, T. Asfour and R. Dillmann. Combining Harris Interest Points and the SIFT Descriptor for Fast Scale-Invariant Object Recognition. In IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), pages 4275–4280, 2009.
[4] P. Azad, T. Asfour and R. Dillmann. Accurate Shape-based 6-DoF Pose Estimation of Single-colored Objects. In IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), pages 2690–2695, 2009.
[3] Jürgen Teich and Sebastian Harl, editors. Invasive Computing. Funding Proposal. DFG Transregional Collaborative Research Centre 89, 2009.
[2] Tobias Weinzierl. A Framework for Parallel PDE Solvers on Multiscale Adaptive Cartesian Grids. Dissertation, Institut für Informatik, Technische Universität München, 2009. [ http ]
[1] Tobias Weinzierl. A Framework for Parallel PDE Solvers on Multiscale Adaptive Cartesian Grids. Dissertation, Technische Universität München, Fakultät für Informatik, 2009.

2008

[6] T. Asfour, K. Welke, P. Azad, A. Ude and R. Dillmann. The Karlsruhe Humanoid Head. In IEEE/RAS International Conference on Humanoid Robots (Humanoids), pages 447–453, December 2008.
[5] Michael Bader. Exploiting the Locality Properties of Peano Curves for Parallel Matrix Multiplication. August 2008.
[4] Mohammad Abdullah Al Faruque, Rudolf Krist and Jörg Henkel. ADAM: Run-time agent-based distributed application mapping for on-chip communication. In Proceedings of the 45th Design Automation Conference (DAC), pages 760–765, June 2008. [ DOI ]
[3] T. Asfour, P. Azad, N. Vahrenkamp, K. Regenstein, A. Bierbaum, K. Welke, J. Schröder and R. Dillmann. Toward Humanoid Manipulation in Human-Centred Environments. Robotics and Autonomous Systems, 56:54–65, 2008.
[2] Jürgen Teich. Invasive Algorithms and Architectures. it - Information Technology, 50(5):300–310, 2008.
[1] N. Vahrenkamp, S. Wieland, P. Azad, D. Gonzalez-Aguirre, T. Asfour and R. Dillmann. Visual Servoing for Humanoid Grasping and Manipulation Tasks. In IEEE/RAS International Conference on Humanoid Robots (Humanoids), pages 406–412, 2008.

2007

[1] Jürgen Becker, Michael Hübner, Gerhard Hettich, Rainer Constapel, Joachim Eisenmann and Jürgen Luka. Dynamic and Partial FPGA Exploitation. Proceedings of the IEEE, 95(2):438–452, February 2007. [ DOI ]