Projects

Z2: Validation and Demonstrator

Principal Investigators:

Prof. Becker, Dr. Hannig, Dr. Wild

Scientific Researchers:

Markus Blocherer, Srinivas Boppu, Joachim Falk, Stephanie Friederich, David May

Abstract

Project Z2 describes the FPGA-based demonstrator platform which will be required a) for early evaluation of invasive hardware, software, and algorithmic concepts, b) reduction of design risks for subsequent ASIC design and development, and c) for prototyping a complete heterogeneous invasive MPSoC as simulation-based approaches alone will not able to cope with this enormous complexity or be not accurate enough.

Synopsis

Often, large scale ASIC designs are prototyped using FPGAs before going into silicon. This is a necessity for the following reasons:

• Early evaluation: An FPGA-based prototyping system is a must for early evaluation of hardware and software concepts of invasive computing. Whereas individual parts might be simulated or prototyped alone, the complex interaction of multiple hardware units and levels of software, however, can only be understood, evaluated and improved on a common demonstrator test bed.
• Prototyping and validation speed-up: In a bottom-up design methodology, individual hardware modules can be functionally verified using simulation tools such as ModelSim from Mentor Graphics, NCsim from Cadence and VCS from Synopsys. This methodology works as long as the design size is limited to just a single processor component. However, RTL simulation will not be possible any more for processor systems including also the complex software for operating system functions and application software. Hence, the above simulation tools are unsuitable for simulating large systems especially when a test case needs to run for a long time. Most of the simulation methods developed in subproject C2 focus on a higher abstraction level in order to explore and validate the concepts of invasive computing, whereas the adequate emulation of a complete MPSoC at register-transfer level may be covered only by a prototyping platform. Prototyping our first invasive MPSoC using FPGA technology is thus a must to provide enough speed and enough accuracy.
• Proof-of-concept: Prototyping also provides a proof-of-functionality in hardware and thus contributes to a safe path to silicon production. Till a few years back, smaller FPGAs were a major obstacle in prototyping large designs. With the advancement in technology, FPGAs have become denser as well as faster. Some high-end FPGAs such as Xilinx Virtex5 LX330 can accommodate about 2 million ASIC gates [1]. Thus, the emulator will be able to prototype not only one component of an InvasIC, but a full complex heterogeneous MPSoC.
• Reduction of design risks: Finally, an FPGA-based prototyping system allows to iteratively make changes to designs of components through reconfiguration of individual parts that may be corrected, refined, or improved with respect to functionality, performance, and area constraints. In all major processor design houses, prototyping is thus a must as changes in silicon and redesigns are often too costly. This reduces design risks for the subsequent ASIC design in the second funding phase enormously.
• Software Co-Development platform for the invasive ASIC: An emulator that allows to map a high gate count is mandatory not only for extensive verification tasks that can be performed tremendously faster than RTL simulation, thus significantly contributing to ASIC risk assessment. In addition, the emulator will be essential for operating system adaptation and driver development for the final invasive MPSoC architecture (the InvasIC), as this task requires fast simulation speed which only emulation can provide.

Approach

Picture showing an example of an invasive architecture and a possible grouping of different compute tiles and iNOC components onto the FPGA-based demonstrator. The grouping of modules as shown in this figure with different shaded boxes is just for conveying the idea of design partitioning. Synopsys CHIPit system is used as FPGA-based demonstrator.

[1] DS100 Virtex-5 Family Overview,
http://www.xilinx.com/support/documentation/data sheets/ds100.pdf, 2009.

Publications